Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Jun Liu; Xiaowei Li 001 (Asian Test Symposium, 2011)

A novel method to mitigate TSV electromigration for 3D ICs. - Yuanqing Cheng; Aida Todri-Sanial; Alberto Bosio; Luigi Dillio; Patrick Girard 001; Arnaud Virazel; Pascal Vivet; Marc Belleville (ISVLSI, 2013)

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2013)

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. - Yuanqing Cheng; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel (ASP-DAC, 2014)

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs. - Jun Zhou 022; Huawei Li 001; Yuntan Fang; Tiancheng Wang; Yuanqing Cheng; Xiaowei Li 001 (ISVLSI, 2014)

A case of precision-tunable STT-RAM memory design for approximate neural network. - Ying Wang 001; Lili Song; Yinhe Han 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (ISCAS, 2015)

A body-biasing of readout circuit for STT-RAM with improved thermal reliability. - Lun Yang; Yuanqing Cheng; Yuhao Wang 002; Hao Yu 001; Weisheng Zhao; Aida Todri-Sanial (ISCAS, 2015)

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM. - Liuyang Zhang; Wang Kang 001; Youguang Zhang; Yuanqing Cheng; Lang Zeng; Jacques-Olivier Klein; Weisheng Zhao (ISVLSI, 2015)

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. - Bi Wu; Yuanqing Cheng; Ying Wang 001; Aida Todri-Sanial; Guangyu Sun 003; Lionel Torres; Weisheng Zhao (NANOARCH, 2015)

Architecture design with STT-RAM: Opportunities and challenges. - Ping Chi; Shuangchen Li; Yuanqing Cheng; Yu Lu; Seung-Hyuk Kang; Yuan Xie 001 (ASP-DAC, 2016)

ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. - Linuo Xue; Yuanqing Cheng; Jianlei Yang 001; Peiyuan Wang; Yuan Xie 001 (ICCAD, 2016)

AES design improvement towards information safety. - Liang Wu; Xiaoxiao Wang 001; Xiaoying Zhao; Yuanqing Cheng; Donglin Su; Aixin Chen; Qihang Shi; Mark Tehranipoor (ISCAS, 2016)

An efficient all-digital IR-Drop Alarmer for DVFS-based SoC. - Liting Yu; Xiaoxiao Wang 001; Yuanqing Cheng; Xiaoying Zhao; Pengyuan Jiao; Aixin Chen; Donglin Su; LeRoy Winemberg; Mehdi Sadi; Mark Tehranipoor (ISCAS, 2016)

Quantitative evaluation of reliability and performance for STT-MRAM. - Liuyang Zhang; Aida Todri-Sanial; Wang Kang 001; Youguang Zhang; Lionel Torres; Yuanqing Cheng; Weisheng Zhao (ISCAS, 2016)

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. - Jianlei Yang 001; Peiyuan Wang; Yaojun Zhang; Yuanqing Cheng; Weisheng Zhao; Yiran Chen 001; Hai (Helen) Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. - Bi Wu; Yuanqing Cheng; Jianlei Yang 001; Aida Todri-Sanial; Weisheng Zhao (IEEE Trans. Reliab., 2016)

Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. - Yuanqing Cheng; Aida Todri-Sanial; Jianlei Yang 001; Weisheng Zhao (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Study of 3-D Power Delivery Networks With Multiple Clock Domains. - Aida Todri-Sanial; Yuanqing Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2016)

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Lei Zhang 008; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Building energy-efficient multi-level cell STT-RAM caches with data compression. - Liu Liu 017; Ping Chi; Shuangchen Li; Yuanqing Cheng; Yuan Xie 001 (ASP-DAC, 2017)

Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. - Bi Wu; Yuanqing Cheng; Pengcheng Dai; Jianlei Yang 001; Youguang Zhang; Dijun Liu; Ying Wang 001; Weisheng Zhao (ICCAD, 2017)

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. - Lili Song; Ying Wang 001; Yinhe Han 001; Huawei Li 001; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs. - Chen Liu; Yuanqing Cheng; Ying Wang 001; Youguang Zhang; Weisheng Zhao (ISCAS, 2018)

Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization. - Bi Wu; Xiaolong Zhang; Yuanqing Cheng; Zhaohao Wang; Dijun Liu; Youguang Zhang; Weisheng Zhao (ISVLSI, 2018)

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. - Yinglin Zhao; Jianlei Yang 001; Weisheng Zhao; Aida Todri-Sanial; Yuanqing Cheng (J. Comput. Sci. Technol., 2018)

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. - Linuo Xue; Bi Wu; Beibei Zhang; Yuanqing Cheng; Peiyuan Wang; Chando Park; Jimmy J. Kan; Seung-Hyuk Kang; Yuan Xie 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design. - Bi Wu; Beibei Zhang; Yuanqing Cheng; Ying Wang 001; Dijun Liu; Weisheng Zhao (IEEE Trans. Very Large Scale Integr. Syst., 2019)

SIP: Boosting Up Graph Computing by Separating the Irregular Property Data. - Jiacheng Ni; Xiaochen Guo; Yuanqing Cheng (ACM Great Lakes Symposium on VLSI, 2020)

Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength. - Wei Wang; Vasilis F. Pavlidis; Yuanqing Cheng (ACM Great Lakes Symposium on VLSI, 2020)

DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. - Jinbo Chen; Keren Liu; Xiaochen Guo; Patrick Girard 001; Yuanqing Cheng (ISQED, 2020)

Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization. - Jiacheng Ni; Keren Liu; Bi Wu; Weisheng Zhao; Yuanqing Cheng; Xiaolong Zhang; Ying Wang 001 (ACM J. Emerg. Technol. Comput. Syst., 2020)

A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. - Bi Wu; Pengcheng Dai; Yuanqing Cheng; Ying Wang 001; Jianlei Yang 001; Zhaohao Wang; Dijun Liu; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. - Bi Wu; Weisheng Zhao; Xiaobo Sharon Hu; Pengcheng Dai; Zhaohao Wang; Chao Wang 094; Ying Wang 001; Jianlei Yang 001; Yuanqing Cheng; Dijun Liu; Youguang Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Taming Process Variations in CNFET for Efficient Last Level Cache Design. - Dawen Xu 002; Zhuangyu Feng; Cheng Liu 008; Li Li; Ying Wang 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (CoRR, 2021)

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. - Patrick Girard 001; Yuanqing Cheng; Arnaud Virazel; Wei Zhao 010; Rajendra Bishnoi; Mehdi B. Tahoori (Proc. IEEE, 2021)

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect. - Jinbo Chen; Chengcheng Lu; Jiacheng Ni; Xiaochen Guo; Patrick Girard 001; Yuanqing Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs. - Kangwei Xu; Yuanqing Cheng (ASP-DAC, 2022)

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. - Fuping Li; Ying Wang 001; Yuanqing Cheng; Yujie Wang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2022)

Thermal Modeling and Design Exploration for Monolithic 3D ICs. - Baoli Peng; Vasilis F. Pavlidis; Yi-Chung Chen; Yuanqing Cheng (ISQED, 2022)

Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective. - Yuanqing Cheng; Xiaochen Guo; Vasilis F. Pavlidis (Integr., 2022)

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits. - Kangwei Xu; Dongrong Zhang; Qiang Ren; Yuanqing Cheng; Patrick Girard 001 (ACM J. Emerg. Technol. Comput. Syst., 2022)

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. - Rongmei Chen; Lin Chen; Jie Liang; Yuanqing Cheng; Souhir Elloumi; Jaehyun Lee; Kangwei Xu; Vihar P. Georgiev; Kai Ni 004; Peter Debacker; Asen Asenov; Aida Todri-Sanial (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization. - Rongmei Chen; Lin Chen; Jie Liang; Yuanqing Cheng; Souhir Elloumi; Jaehyun Lee; Kangwei Xu; Vihar P. Georgiev; Kai Ni 004; Peter Debacker; Asen Asenov; Aida Todri-Sanial (IEEE Trans. Very Large Scale Integr. Syst., 2022)

TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning. - Wei W. Xing; Zheng Xing; Rongqi Lu; Zhelong Wang; Ning Xu; Yuanqing Cheng; Weisheng Zhao (DAC, 2023)

OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits. - Yanfang Liu; Guohao Dai; Yuanqing Cheng; Wang Kang 001; Wei W. Xing (ICCAD, 2023)

3D SRAM Design & Optimization with Open Source Memory Compiler. - Sunan Chen; Chao Wu; Yunlang Cai; Yuan Guan; Yuanqing Cheng (3DIC, 2024)

BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization. - Hang Wu; Ning Xu; Wei W. Xing; Yuanqing Cheng (ASPDAC, 2024)

MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction. - Mingyue Wang; Yuanqing Cheng; Yage Lin; Kelin Peng; Shunchuan Yang; Zhou Jin 001; Wei W. Xing (DAC, 2024)

ARO: Autoregressive Operator Learning for Transferable and Multi-fidelity 3D-IC Thermal Analysis With Active Learning. - Mingyue Wang; Yuanqing Cheng; Weiheng Zeng; Zhenjie Lu; Vasilis F. Pavlidis; Wei Xing (ICCAD, 2024)

PDG: A Prefetcher for Dynamic Graph Updating. - Xinmiao Zhang 004; Cheng Liu 008; Jiacheng Ni; Yuanqing Cheng; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs. - Wei W. Xing; Longze Wang; Zhelong Wang; Zhaoyu Shi; Ning Xu; Yuanqing Cheng; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Cool3D: Cost-Optimized and Efficient Liquid Cooling for 3D Integrated Circuits. - Jing Li; Bingrui Zhang; Yuquan Sun; Wei Xing; Yuanqing Cheng (DATE, 2025)

A Comprehensive Inductance-Aware Modeling Approach to Power Distribution Network in Heterogeneous 3D Integrated Circuits. - Quansen Wang; Vasilis F. Pavlidis; Yuanqing Cheng (DATE, 2025)

Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuits. - Quansen Wang; Vasilis F. Pavlidis; Xuning Feng; Rui Wang; Wei Zhang; Yuanqing Cheng (ISVLSI, 2025)

PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization. - Yiyu Wang; Vasilis F. Pavlidis; Rui Wang; Yuanqing Cheng (ISVLSI, 2025)

Testing and fault tolerance techniques for carbon nanotube-based FPGAs. - Siyuan Lu; Kangwei Xu; Peng Xie; Rui Wang; Yuanqing Cheng (Integr., 2025)