Yuanwei Fang

According to our database, Yuanwei Fang authored at least 13 papers between 2012 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

KPerfIR: Towards an Open and Compiler-centric Ecosystem for GPU Kernel Performance Tooling on Modern AI Workloads.

Yue Guan, Yuanwei Fang, Keren Zhou, Corbin Robeck, Manman Ren, Zhongkai Yu, Yufei Ding, Adnan Aziz

CoRR, May, 2025

Mercury: Unlocking Multi-GPU Operator Optimization for LLMs via Remote Memory Scheduling.

Yue Guan, Xinwei Qiang, Zaifeng Pan, Daniels Johnson, Yuanwei Fang, Keren Zhou, Yuke Wang, Wanlu Li, Yufei Ding, Adnan Aziz

Proceedings of the ACM SIGOPS 31st Symposium on Operating Systems Principles, 2025

KPerfIR: Towards a Open and Compiler-centric Ecosystem for GPU Kernel Performance Tooling on Modern AI Workloads.

Yue Guan, Yuanwei Fang, Keren Zhou, Corbin Robeck, Manman Ren, Zhongkai Yu, Yufei Ding, Adnan Aziz

Proceedings of the 19th USENIX Symposium on Operating Systems Design and Implementation, 2025

2023

NPS: A Framework for Accurate Program Sampling Using Graph Neural Network.

Yuanwei Fang, Zihao Liu, Yanheng Lu, Jiawei Liu, Jiajie Li, Yi Jin, Jian Chen, Yen-Kuang Chen, Hongzhong Zheng, Yuan Xie

CoRR, 2023

2022

184QPS/W 64Mb/mm²3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.

Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.

Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du, Fei Xue, Yuanwei Fang, Hongzhong Zheng, Yuan Xie

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2019

Accelerating Raw Data Analysis with the ACCORDA Software and Hardware Architecture.

Yuanwei Fang, Chen Zou, Andrew A. Chien

Proc. VLDB Endow., 2019

Programmable Acceleration for Sparse Matrices in a Data-Movement Limited World.

Arjun Rawal, Yuanwei Fang, Andrew A. Chien

Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2017

UDP: a programmable accelerator for extract-transform-load workloads and more.

Yuanwei Fang, Chen Zou, Aaron J. Elmore, Andrew A. Chien

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016

Performance of parallel prefix circuit transition localization of pulsed waveforms.

Yuanwei Fang, Andrew A. Chien, Andrew Lehane, Lee Barford

Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2016

2015

10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture.

Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati

SIGARCH Comput. Archit. News, 2015

Fast support for unstructured data processing: the unified automata processor.

Yuanwei Fang, Tung Thanh Hoang, Michela Becchi, Andrew A. Chien

Proceedings of the 48th International Symposium on Microarchitecture, 2015

2012

A novel hardware-oriented decoding algorithm for non-binary LDPC codes.

Hong Yang, Qingqing Yang, Yuanwei Fang, Xiaofang Zhou, Gerald E. Sobelman

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012