Trace Buffer Attack: Security versus observability study in post-silicon debug. - Yuanwen Huang; Anupam Chattopadhyay; Prabhat Mishra 001 (VLSI-SoC, 2015)

MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection. - Yuanwen Huang; Swarup Bhunia; Prabhat Mishra 001 (CCS, 2016)

Reliability and energy-aware cache reconfiguration for embedded systems. - Yuanwen Huang; Prabhat Mishra 001 (ISQED, 2016)

Trojan localization using symbolic algebra. - Farimah Farahmandi; Yuanwen Huang; Prabhat Mishra 001 (ASP-DAC, 2017)

Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems. - Yuanwen Huang; Prabhat Mishra 001 (ICCD, 2017)

Trace Buffer Attack on the AES Cipher. - Yuanwen Huang; Prabhat Mishra 001 (J. Hardw. Syst. Secur., 2017)

An automated configurable Trojan insertion framework for dynamic trust benchmarks. - Jonathan Cruz 001; Yuanwen Huang; Prabhat Mishra 001; Swarup Bhunia (DATE, 2018)

Scalable Test Generation for Trojan Detection Using Side Channel Analysis. - Yuanwen Huang; Swarup Bhunia; Prabhat Mishra 001 (IEEE Trans. Inf. Forensics Secur., 2018)

Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems. - Yuanwen Huang; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization. - Alif Ahmed; Yuanwen Huang; Prabhat Mishra 001 (ACM Trans. Embed. Comput. Syst., 2019)

Vulnerability-aware Dynamic Reconfiguration of Partially Protected Caches. - Yuanwen Huang; Prabhat Mishra 001 (ISQED, 2020)