CORDIC-Based Architecture for Computing Nth Root and Its Implementation. - Yuanyong Luo; Yuxuan Wang; Huaqing Sun; Yi Zha; Zhongfeng Wang 001; Hongbing Pan (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

CLA Formula Aided Fast Architecture Design for Clustered Look-Ahead Pipelined IIR Digital Filter. - Yuanyong Luo; Hongbing Pan; Qinghong Shen; Zhongfeng Wang 001 (SiPS, 2019)

Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base. - Yuanyong Luo; Yuxuan Wang; Yajun Ha; Zhongfeng Wang 001; Siyuan Chen; Hongbing Pan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base". - Yuanyong Luo; Yuxuan Wang; Yajun Ha; Zhongfeng Wang 001; Siyuan Chen; Hongbing Pan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions. - Hui Chen 015; Lin Jiang; Yuanyong Luo; Zhonghai Lu; Yuxiang Fu; Li Li 003; Zongguang Yu (ISCAS, 2020)

An Optimized Compression Strategy for Compressor-Based Approximate Multiplier. - Manzhen Wang; Yuanyong Luo; Mengyu An; Yuou Qiu; Muhan Zheng; Zhongfeng Wang 001; Hongbing Pan (ISCAS, 2020)

A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions. - Huaqing Sun; Yuanyong Luo; Yajun Ha; Yinghuan Shi; Yang Gao 001; Qinghong Shen; Hongbing Pan (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions. - Hongxi Dong; Manzhen Wang; Yuanyong Luo; Muhan Zheng; Mengyu An; Yajun Ha; Hongbing Pan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number. - Yuxuan Wang; Yuanyong Luo; Zhongfeng Wang 001; Qinghong Shen; Hongbing Pan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Effective Plug-Ins for Reducing Inference-Latency of Spiking Convolutional Neural Networks During Inference Phase. - Xuan Chen; Xiaopeng Yuan; Gaoming Fu; Yuanyong Luo; Tao Yue 003; Feng Yan 002; Yuxuan Wang; Hongbing Pan (Frontiers Comput. Neurosci., 2021)

Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers. - Fei Lyu 002; Xiaoqi Xu; Yu Wang 161; Yuanyong Luo; Yuxuan Wang; Hongbing Pan (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers. - Fei Lyu 002; Zhelong Mao; Jin Zhang; Yu Wang 161; Yuanyong Luo (IEEE Trans. Very Large Scale Integr. Syst., 2021)

CLA Formula and its Acceleration of Architecture Design for Clustered Look-Ahead Pipelined Recursive Digital Filter. - Muhan Zheng; Yuanyong Luo; Hongbing Pan; Zhongfeng Wang 001; Yuan Xue (J. Signal Process. Syst., 2021)

Reconfigurable Multifunction Computing Unit Using an Universal Piecewise Linear Method. - Fei Lyu 002; Jian Chen; Shuo Huang; Wenxiu Wang; Yuanyong Luo; Yu Wang 161 (ISCAS, 2022)

An optimized hardware implementation of the CORDIC algorithm. - Fei Lyu 002; Chaoran Wu; Yuxuan Wang; Hongbing Pan; Yu Wang 161; Yuanyong Luo (IEICE Electron. Express, 2022)

ML-PLAC: Multiplierless Piecewise Linear Approximation for Nonlinear Function Evaluation. - Fei Lyu 002; Yan Xia; Zhelong Mao; Yanxu Wang; Yu Wang 161; Yuanyong Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers. - Fei Lyu 002; Yan Xia; Yuheng Chen; Yanxu Wang; Yuanyong Luo; Yu Wang 161 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An Optimized Architecture for Computing the Square Root of Complex Numbers. - Yu Wang 161; Haoyu Zhang; Wei Hu; Xin Zhang; Xinyu Tian; Fei Lyu 002; Yuanyong Luo (ISCAS, 2024)

Ascend HiFloat8 Format for Deep Learning. - Yuanyong Luo; Zhongxing Zhang; Richard Wu; Hu Liu; Ying Jin; Kai Zheng; Minmin Wang; Zhanying He; Guipeng Hu; Luyao Chen; Tianchi Hu; Junsong Wang; et al. (CoRR, 2024)

FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation. - Yu Wang 161; Xingcheng Liang; Shuai Niu; Chi Zhang; Fei Lyu 002; Yuanyong Luo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Universal Methodology of Complex Number Computation for Low-Complexity and High-Speed Implementation. - Yu Wang 161; Jin Zhang; Youlong Wu; Fei Lyu 002; Yuanyong Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An Efficient Methodology for Binary Logarithmic Computations of Floating-Point Numbers With Normalized Output Within One ulp of Accuracy. - Fei Lyu 002; Yuanyong Luo; Weiqiang Liu 001 (IEEE Trans. Computers, 2025)