A Novel Approach to Detect Smile Expression. - Yuanzhi Zhang 004; Li Zhou; Tao Sun (ICMLA (1), 2012)

A 5.8 GHz DSRC digitally controlled CMOS RF-SoC transceiver for China ETC. - Huimin Liu; Xiongfei Qu; Lingling Cao; Ruifeng Liu; Yuanzhi Zhang 004; Meijuan Zhang; Xiaoqiang Li; Wenshen Wang; Chao Lu 005 (ASP-DAC, 2018)

A 1.2 V supply 0.58 ppm/°C CMOS bandgap voltage reference. - Jinlong Hu 003; Huachao Xu; Yuanzhi Zhang 004; Jie Sun; Tao Du; Chao Lu 005; Guofeng Li (IEICE Electron. Express, 2018)

A 2.1-ppm/°C all-MOSFET voltage reference with a 1.2-V supply voltage. - Huachao Xu; Yuanzhi Zhang 004; Ke Liang 003; Jinlong Hu 003; Chao Lu 005; Guofeng Li (IEICE Electron. Express, 2018)

98 pA, 0.17 ppm/V, -72 dB@100 Hz voltage reference for Internet-of-Things systems. - Huachao Xu; Yuanzhi Zhang 004; Ke Liang 003; Jin Wang; Chao Lu 005; Guofeng Li (IEICE Electron. Express, 2018)

A 5.8 GHz Digitally Controlled CMOS Receiver With a Wide Dynamic Range for Chinese ETC System. - Lingling Cao; Ruifeng Liu; Yuanzhi Zhang 004; Meijuan Zhang; Xiaoqiang Li; Wenshen Wang; Huimin Liu; Chao Lu 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Race-Condition-Aware and Hardware-Oriented Task Partitioning and Scheduling Using Entropy Maximization. - Sizhao Li; Yuanzhi Zhang 004; Hongyin Luo; Yan Chen; Chao Lu 005; Donghui Guo (IEEE Trans. Parallel Distributed Syst., 2018)

A 5.8 GHz digitally configurable DSRC RF-SoC transmitter for China ETC systems. - Xiongfei Qu; Ruifeng Liu; Lingling Cao; Yuanzhi Zhang 004; Wenshen Wang; Huimin Liu; Chao Lu 005 (Integr., 2019)

An all-digital frequency tunable IR-UWB transmitter with an approximate 15th derivative Gaussian pulse generator. - Baolin Wei; Tian Chen; Chao Lu 005; Weilin Xu; Yuanzhi Zhang 004; Xueming Wei; Hongwei Yue; Jihai Duan (Integr., 2019)

A Highly Parallel Hardware Architecture of Table-Based CABAC Bit Rate Estimator in an HEVC Intra Encoder. - Yuanzhi Zhang 004; Chao Lu 005 (IEEE Trans. Circuits Syst. Video Technol., 2019)

High-Performance Algorithm Adaptations and Hardware Architecture for HEVC Intra Encoders. - Yuanzhi Zhang 004; Chao Lu 005 (IEEE Trans. Circuits Syst. Video Technol., 2019)

Efficient Algorithm Adaptations and Fully Parallel Hardware Architecture of H.265/HEVC Intra Encoder. - Yuanzhi Zhang 004; Chao Lu 005 (IEEE Trans. Circuits Syst. Video Technol., 2019)