HPPU: An Energy-Efficient Sparse DNN Training Processor with Hybrid Weight Pruning. - Yang Wang 089; Yubin Qin; Leibo Liu; Shaojun Wei; Shouyi Yin (AICAS, 2021)

A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation. - Yang Wang 089; Yubin Qin; Dazheng Deng; Jingchuan Wei; Tianbao Chen; Xinhan Lin; Leibo Liu; Shaojun Wei; Shouyi Yin (VLSI Circuits, 2021)

A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing. - Yang Wang 089; Yubin Qin; Dazheng Deng; Jingchuan Wei; Yang Zhou; Yuanqi Fan; Tianbao Chen; Hao Sun; Leibo Liu; Shaojun Wei; Shouyi Yin (ISSCC, 2022)

Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning. - Yang Wang 089; Yubin Qin; Dazheng Deng; Jingchuan Wei; Tianbao Chen; Xinhan Lin; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE J. Solid State Circuits, 2022)

SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning. - Yang Wang 089; Yubin Qin; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

BR-CIM: An Efficient Binary Representation Computation-In-Memory Design. - Zhiheng Yue; Yabing Wang; Yubin Qin; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination. - Yubin Qin; Yang Wang 089; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Yang Zhou; Yuanqi Fan; Jingchuan Wei; Tianbao Chen; Leibo Liu; Shaojun Wei; Yang Hu 001; et al. (A-SSCC, 2023)

FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction. - Yubin Qin; Yang Wang 089; Dazheng Deng; Zhiren Zhao; Xiaolong Yang; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISCA, 2023)

A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing. - Yang Wang 089; Yubin Qin; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2023)

An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention. - Yang Wang 089; Yubin Qin; Dazheng Deng; Jingchuan Wei; Yang Zhou; Yuanqi Fan; Tianbao Chen; Hao Sun; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

A 28nm 118.26TOPS/W Multi-Dimensional Fault-Tolerant Al Processor Enabling Voltage-Frequency Scaling Below Point-of-First-Failure. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Shaojun Wei; Yang Hu 001; Shouyi Yin (A-SSCC, 2024)

FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing. - Xiaolong Yang; Yang Wang 089; Yubin Qin; Jiachen Wang; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition. - Yubin Qin; Yang Wang 089; Zhiren Zhao; Xiaolong Yang; Yang Zhou; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISCA, 2024)

Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. - Zhiheng Yue; Huizheng Wang; Jiahao Fang; Jinyi Deng; Guangyang Lu; Fengbin Tu; Ruiqi Guo; Yuxuan Li; Yubin Qin; Yang Wang 089; Chao Li 009; Huiming Han; et al. (ISCA, 2024)

20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models. - Ruiqi Guo; Lei Wang; Xiaofeng Chen; Hao Sun; Zhiheng Yue; Yubin Qin; Huiming Han; Yang Wang 089; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. - Huizheng Wang; Jiahao Fang; Xinru Tang; Zhiheng Yue; Jinxi Li; Yubin Qin; Sihan Guan; Qinze Yang; Yang Wang 089; Chao Li 009; Yang Hu 001; Shouyi Yin (MICRO, 2024)

A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication. - Yubin Qin; Yang Wang 089; Xiaolong Yang; Zhiren Zhao; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. - Huizheng Wang; Jiahao Fang; Xinru Tang; Zhiheng Yue; Jinxi Li; Yubin Qin; Sihan Guan; Qize Yang; Yang Wang 089; Chao Li 009; Yang Hu 001; Shouyi Yin (CoRR, 2024)

Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow. - Yubin Qin; Yang Wang 089; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Yang Zhou; Yuanqi Fan; Jingchuan Wei; Tianbao Chen; Leibo Liu; Shaojun Wei; Yang Hu 001; et al. (IEEE J. Solid State Circuits, 2024)

23.8 An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation. - Yubin Qin; Yang Wang 089; Jiachen Wang; Zhiwei Lin; Yushu Zhao; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2025)

BeaCIM: A Digital Compute-in-Memory DNN Processor With Bi-Directional Exponent Alignment for FP8 Training. - Yang Zhou; Yang Wang 089; Wenxin Yin; Yazheng Jiang; Jingchuan Wei; Yubin Qin; Yang Hu 001; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

VideoHallu: Evaluating and Mitigating Multi-modal Hallucinations on Synthetic Video Understanding. - Zongxia Li; Xiyang Wu; Guangyao Shi; Yubin Qin; Hongyang Du; Tianyi Zhou 001; Dinesh Manocha; Jordan Lee Boyd-Graber (CoRR, 2025)

An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2025)