A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA. - Mingqiang Huang; Yucen Liu; Quan Cheng; Shuxin Yang; Kai Li 024; Junyi Luo; Zhengke Yang; Qiufeng Li; Hao Yu 001; Changhai Man (FPGA, 2022)

A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks. - Mingqiang Huang; Yucen Liu; Changhai Man; Kai Li 024; Quan Cheng; Wei Mao 002; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme. - Mingqiang Huang; Yucen Liu; Sixiao Huang; Kai Li 024; Qiuping Wu; Hao Yu 001 (FPGA, 2023)