A high-level synthesis approach for precisely-timed, energy-efficient embedded systems. - Yuchao Liao; Tosiron Adegbija; Roman Lysecky (Sustain. Comput. Informatics Syst., 2022)

Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning. - Yuchao Liao; Tosiron Adegbija; Roman Lysecky (ASP-DAC, 2023)

Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning. - Yuchao Liao; Tosiron Adegbija; Roman Lysecky; Ravi Tandon (ACM Great Lakes Symposium on VLSI, 2024)

Are LLMs Any Good for High-Level Synthesis? - Yuchao Liao; Tosiron Adegbija; Roman Lysecky (ICCAD, 2024)

Deep Inverse Design for High-Level Synthesis. - Ping Chang; Tosiron Adegbija; Yuchao Liao; Claudio Talarico; Ao Li 004; Janet Roveda (CoRR, 2024)

System-Level Design Space Exploration for High-Level Synthesis Under End-to-End Latency Constraints. - Yuchao Liao; Tosiron Adegbija; Roman Lysecky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)