VLSI floorplanning with boundary constraints based on corner block list. - Yuchun Ma; Sheqin Dong; Xianlong Hong; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2001)

Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Yici Cai; Chung-Kuan Cheng; Jun Gu (DAC, 2001)

Floorplanning with abutment constraints based on corner block list. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Yici Cai; Chung-Kuan Cheng; Jun Gu (Integr., 2001)

A buffer planning algorithm based on dead space redistribution. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2003)

Dynamic global buffer planning optimization based on detail block locating and congestion analysis. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Yici Cai; Chung-Kuan Cheng; Jun Gu (DAC, 2003)

Evaluating a bounded slice-line grid assignment in O(nlogn) time. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (ISCAS (4), 2003)

Arbitrary convex and concave rectilinear block packing based on corner block list. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Yici Cai; Song Chen 001; Chung-Kuan Cheng; Jun Gu (ISCAS (5), 2003)

An integrated floorplanning with an efficient buffer planning algorithm. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Yici Cai; Chung-Kuan Cheng; Jun Gu (ISPD, 2003)

A buffer planning algorithm with congestion optimization. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2004)

Buffer allocation algorithm with consideration of routing congestion. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2004)

A buffer planning algorithm for chip-level floorplanning. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (Sci. China Ser. F Inf. Sci., 2004)

Corner block list representation and its application with boundary constraints. - Xianlong Hong; Yuchun Ma; Sheqin Dong; Yici Cai; Chung-Kuan Cheng; Jun Gu (Sci. China Ser. F Inf. Sci., 2004)

Fast Evaluation of Bounded Slice-Line Grid. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Chung-Kuan Cheng; Jun Gu (J. Comput. Sci. Technol., 2004)

Stairway compaction using corner block list and its applications with rectilinear blocks. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Yici Cai; Chung-Kuan Cheng; Jun Gu (ACM Trans. Design Autom. Electr. Syst., 2004)

VLSI block placement with alignment constraints based on corner block list. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Chung-Kuan Cheng (ISCAS (6), 2005)

Performance constrained floorplanning based on partial clustering [IC layout]. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Chung-Kuan Cheng (ISCAS (2), 2005)

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Chung-Kuan Cheng (ISQED, 2005)

Buffer Planning Algorithm Based on Partial Clustered Floorplanning. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Chung-Kuan Cheng (ISQED, 2005)

Buffer planning as an Integral part of floorplanning with consideration of routing congestion. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Chung-Kuan Cheng; Jun Gu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. - Liu Yang; Sheqin Dong; Xianlong Hong; Yuchun Ma (APCCAS, 2006)

An automated design flow for 3D microarchitecture evaluation. - Jason Cong; Ashok Jagannathan; Yuchun Ma; Glenn Reinman; Jie Wei; Yan Zhang (ASP-DAC, 2006)

General Floorplans with L/T-Shaped Blocks Using Corner Block List. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Chung-Kuan Cheng; Jun Gu (J. Comput. Sci. Technol., 2006)

VLSI Block Placement With Alignment Constraints. - Song Chen 001; Sheqin Dong; Xianlong Hong; Yuchun Ma; Chung-Kuan Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. - Jiayi Liu; Sheqin Dong; Yuchun Ma; Di Long; Xianlong Hong (ASP-DAC, 2007)

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. - Yuchun Ma; Zhuoyuan Li 003; Jason Cong; Xianlong Hong; Glenn Reinman; Sheqin Dong; Qiang Zhou 001 (ASP-DAC, 2007)

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. - Pingqiang Zhou; Yuchun Ma; Qiang Zhou 001; Xianlong Hong (CAD/Graphics, 2007)

An effective buffer planning algorithm for IP based fixed-outline SOC placement. - Ou He; Sheqin Dong; Jinian Bian; Yuchun Ma; Xianlong Hong (ACM Great Lakes Symposium on VLSI, 2007)

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. - Pingqiang Zhou; Yuchun Ma; Zhuoyuan Li 003; Robert P. Dick; Li Shang; Hai Zhou 001; Xianlong Hong; Qiang Zhou 001 (ICCAD, 2007)

Fine grain 3D integration for microarchitecture design through cube packing exploration. - Yongxiang Liu; Yuchun Ma; Eren Kursun; Glenn Reinman; Jason Cong (ICCD, 2007)

A Fast 3D-BSG Algorithm for 3D Packing Problem. - Lingyi Zhang; Sheqin Dong; Xianlong Hong; Yuchun Ma (ISCAS, 2007)

Interconnect Power Optimization Based on Timing Analysis. - Liu Yang; Sheqin Dong; Yuchun Ma; Xianlong Hong (ISVLSI, 2007)

An accurate and efficient probabilistic congestion estimation model in x architecture. - Yaoguang Wei; Sheqin Dong; Xianlong Hong; Yuchun Ma (SLIP, 2007)

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. - Xin Li; Yuchun Ma; Xianlong Hong; Sheqin Dong; Jason Cong (ASP-DAC, 2008)

MRAPF: Minimum RTT Asymmetric-Path First for Mobile Multi-homed End-to-End Transfer. - Jiemin Liu; Yuchun Ma; Yuan Gao (FSKD (4), 2008)

IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. - Xiang Qiu; Yuchun Ma; Xiangqing He; Xianlong Hong (ISQED, 2008)

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. - Yuchun Ma; Yongxiang Liu; Eren Kursun; Glenn Reinman; Jason Cong (ACM J. Emerg. Technol. Comput. Syst., 2008)

A novel thermal optimization flow using incremental floorplanning for 3D ICs. - Xin Li; Yuchun Ma; Xianlong Hong (ASP-DAC, 2009)

Multi-objective Floorplanning Based on Fuzzy Logic. - Fubing Mao; Yuchun Ma; Ning Xu 006; Xianlong Hong; Yu Wang 002 (FSKD (4), 2009)

Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. - Xiaoming Chen 003; Yu Wang 002; Yu Cao 001; Yuchun Ma; Huazhong Yang (ISLPED, 2009)

Simultaneous buffer and interlayer via planning for 3D floorplanning. - Xu He; Sheqin Dong; Yuchun Ma; Xianlong Hong (ISQED, 2009)

Incremental power optimization for multiple supply voltage design. - Yuchun Ma; Xiang Qiu; Xiangqing He; Xianlong Hong (ISQED, 2009)

Modern Floorplanning with Boundary Clustering Constraint. - Li Li; Yuchun Ma; Ning Xu 006; Yu Wang 002; Xianlong Hong (ISVLSI, 2009)

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation. - Yuchun Ma; Xin Li 001; Yu Wang 002; Xianlong Hong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. - Li Li; Yuchun Ma; Ning Xu 006; Yu Wang 002; Xianlong Hong (ASP-DAC, 2010)

Simultaneous slack budgeting and retiming for synchronous circuits optimization. - Shenghua Liu; Yuchun Ma; Xianlong Hong; Yu Wang 002 (ASP-DAC, 2010)

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. - Xu He; Sheqin Dong; Yuchun Ma (Integr., 2010)

Thermal Impacts of Leakage Power in 2D/3D floorplanning. - Yuchun Ma; Qiang Zhou 001; Pingqiang Zhou; Xianlong Hong (J. Circuits Syst. Comput., 2010)

Incremental layout optimization for NoC designs based on MILP formulation. - Jia Liu 025; Yuchun Ma; Ning Xu 006; Yu Wang 002 (ASICON, 2011)

On-chip hybrid power supply system for wireless sensor nodes. - Wulong Liu; Yu Wang 002; Wei Liu 015; Yuchun Ma; Yuan Xie 001; Huazhong Yang (ASP-DAC, 2011)

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. - Kan Wang; Yuchun Ma; Sheqin Dong; Yu Wang 002; Xianlong Hong; Jason Cong (ASP-DAC, 2011)

Network flow-based simultaneous retiming and slack budgeting for low power design. - Bei Yu 001; Sheqin Dong; Yuchun Ma; Tao Lin; Yu Wang 002; Song Chen 001; Satoshi Goto (ASP-DAC, 2011)

Tree-Based Partitioning Approach for Network-on-Chip Synthesis. - Binjie Song; Shan Zeng; Yuchun Ma; Ning Xu 006; Yu Wang 002 (CAD/Graphics, 2011)

Novel and efficient min cut based voltage assignment in gate level. - Tao Lin; Sheqin Dong; Song Chen 001; Yuchun Ma; Ou He; Satoshi Goto (ISQED, 2011)

Circuit-level delay modeling considering both TDDB and NBTI. - Hong Luo; Xiaoming Chen 003; Jyothi Velamala; Yu Wang 002; Yu Cao 001; Vikas Chandra; Yuchun Ma; Huazhong Yang (ISQED, 2011)

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. - Kan Wang; Sheqin Dong; Yuchun Ma; Yu Wang 002; Xianlong Hong; Jason Cong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. - Ruining He; Guoqiang Liang; Yuchun Ma; Yu Wang 002; Jinian Bian (ARC, 2012)

Thermal-aware power network design for IR drop reduction in 3D ICs. - Zuowei Li; Yuchun Ma; Qiang Zhou 001; Yici Cai; Yu Wang 002; Tingting Huang; Yuan Xie 001 (ASP-DAC, 2012)

ISBA: An independent set-based algorithm for automated partial reconfiguration module generation. - Ruining He; Yuchun Ma; Kang Zhao; Jinian Bian (ICCAD, 2012)

SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator. - Zhongda Yuan; Yuchun Ma; Jinian Bian (IPDPS Workshops, 2012)

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. - Kan Wang; Sheqin Dong; Yuchun Ma; Satoshi Goto; Jason Cong (ISQED, 2012)

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits. - Hong Luo; Yu Wang 002; Yu Cao 001; Yuan Xie 001; Yuchun Ma; Huazhong Yang (ISVLSI, 2012)

Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization. - Xiaoming Chen 003; Yu Wang 002; Yu Cao 001; Yuchun Ma; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Incremental 3D NoC synthesis based on physical-aware router merging algorithm. - Yuanyuan Li; Ning Xu 006; Yuchun Ma; Jinian Bian (ASICON, 2013)

Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs. - Jixin Zhang; Ning Xu 006; Yuchun Ma; Yu Wang 002; Jinian Bian (ASICON, 2013)

HS3DPG: Hierarchical simulation for 3D P/G network. - Shuai Tao; Xiaoming Chen 003; Yu Wang 002; Yuchun Ma; Yiyu Shi 001; Hui Wang 004; Huazhong Yang (ASP-DAC, 2013)

Efficient custom instruction generation based on characterizing of basic blocks. - Guoqiang Liang; Yuchun Ma; Kang Zhao; Jinian Bian (CSCWD, 2013)

Automatic enhanced CDFG generation based on runtime instrumentation. - Zhongda Yuan; Yuchun Ma; Jinian Bian; Kang Zhao (CSCWD, 2013)

TSV-aware topology generation for 3D Clock Tree Synthesis. - Wulong Liu; Haixiao Du; Yu Wang 002; Yuchun Ma; Yuan Xie 001; Jinguo Quan; Huazhong Yang (ISQED, 2013)

Whitespace-aware TSV arrangement in 3D clock tree synthesis. - Xin Li 001; Wulong Liu; Haixiao Du; Yu Wang 002; Yuchun Ma; Huazhong Yang (ISVLSI, 2013)

RALP: Reconvergence-aware layer partitioning for 3D FPGAs. - Qingyu Liu; Yuchun Ma; Yu Wang 002; Wayne Luk; Jinian Bian (ReConFig, 2013)

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits. - Xiaoming Chen 003; Hong Luo; Yu Wang 002; Yu Cao 001; Yuan Xie 001; Yuchun Ma; Huazhong Yang (IET Circuits Devices Syst., 2013)

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. - Zuowei Li; Yuchun Ma; Qiang Zhou 001; Yici Cai; Yuan Xie 001; Tingting Huang (Integr., 2013)

Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. - Ruining He; Guoqiang Liang; Yuchun Ma; Yu Wang 002; Jinian Bian (J. Circuits Syst. Comput., 2013)

Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs. - Ning Xu 006; Yuchun Ma; Jia Liu 025; Shou-Chun Tao (J. Comput. Sci. Technol., 2013)

A universal FPGA-based floating-point matrix processor for mobile systems. - Wenqiang Wang; Kaiyuan Guo; Mengyuan Gu; Yuchun Ma; Yu Wang 002 (FPT, 2014)

HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs. - Yuchun Ma; Jinglan Liu; Chao Zhang; Wayne Luk (ICCD, 2014)

Efficient region-aware P/G TSV planning for 3D ICs. - Song Yao; Xiaoming Chen 003; Yu Wang 002; Yuchun Ma; Yuan Xie 001; Huazhong Yang (ISQED, 2014)

On-Chip Hybrid Power Supply System for Wireless Sensor Nodes. - Wulong Liu; Yu Wang 002; Yuchun Ma; Yuan Xie 001; Huazhong Yang (ACM J. Emerg. Technol. Comput. Syst., 2014)

HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric. - Chao Zhang; Yuchun Ma; Wayne Luk (CAD/Graphics, 2015)

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis. - Wulong Liu; Yu Wang 002; Guoqing Chen; Yuchun Ma; Yuan Xie 001; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2015)

HS3-DPG: Hierarchical Simulation for 3-D P/G Network. - Yu Wang 002; Song Yao; Shuai Tao; Xiaoming Chen 003; Yuchun Ma; Yiyu Shi 001; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Relation-oriented resource allocation for multi-accelerator systems. - Teng Yu; Bo Feng; Mark Stillwell; José Gabriel F. Coutinho; Wenlai Zhao; Shuang Liang 012; Wayne Luk; Alexander L. Wolf; Yuchun Ma (ASAP, 2016)

F-CNN: An FPGA-based framework for training Convolutional Neural Networks. - Wenlai Zhao; Haohuan Fu; Wayne Luk; Teng Yu; Shaojun Wang; Bo Feng; Yuchun Ma; Guangwen Yang (ASAP, 2016)

Modular Placement for Interposer based Multi-FPGA Systems. - Fubing Mao; Wei Zhang 012; Bo Feng; Bingsheng He; Yuchun Ma (ACM Great Lakes Symposium on VLSI, 2016)

Intelligent Composition of Test Papers based on MOOC Learning Data. - Lin Ma; Yuchun Ma (EDM, 2017)

基于MPSoC并行调度的矩阵乘法加速算法研究 (Research on Acceleration of Matrix Multiplication Based on Parallel Scheduling on MPSoC). - Fei Yang; Yuchun Ma; Jin Hou; Ning Xu 006 (计算机科学, 2017)

Lattice-Based Scheduling for Multi-FPGA Systems. - Teng Yu; Bo Feng; Mark Stillwell; Liucheng Guo; Yuchun Ma; John Thomson (FPT, 2018)

Shift-based Primitives for Efficient Convolutional Neural Networks. - Huasong Zhong; Xianggen Liu; Yihui He; Yuchun Ma (CoRR, 2018)

AddressNet: Shift-Based Primitives for Efficient Convolutional Neural Networks. - Yihui He; Xianggen Liu; Huasong Zhong; Yuchun Ma (WACV, 2019)

SNEGAN: Signed Network Embedding by Using Generative Adversarial Nets. - Lijia Ma; Yuchun Ma; Qiuzhen Lin; Junkai Ji; Carlos A. Coello Coello; Maoguo Gong (IEEE Trans. Emerg. Top. Comput. Intell., 2022)

Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow. - Kang Zhao; Yuchun Ma; Ruining He; Jixing Zhang; Ning Xu 006; Jinian Bian (ACM Trans. Reconfigurable Technol. Syst., 2023)

Iterative Design of a Teaching Assistant Training Program in Computer Science Using the Agile Method. - Runda Liu; Shengqi Chen 001; Jiajie Chen; Songjie Niu; Yuchun Ma; Xiaofeng Tang (SIGCSE (1), 2025)

Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration. - Yongxiang Liu; Yuchun Ma; Eren Kurshan; Glenn Reinman; Jason Cong (CoRR, 2025)