A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS. - Yudong Zhang 006; Woogeun Rhee; Taeik Kim; Hojin Park; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS. - Yudong Zhang 006; Xiaofeng Liu; Woogeun Rhee; Hanjun Jiang; Zhihua Wang 001 (ISCAS, 2017)

A Reconfigurable Architecture Using a Flexible LO Modulator to Unify High-Sensitivity Signal Reception and Compressed-Sampling Wideband Signal Detection. - Tanbir Haque; Matthew Bajor; Yudong Zhang 006; Jianxun Zhu; Zarion A. Jacobs; Blayne Kettlewell; John Wright 001; Peter R. Kinget (IEEE J. Solid State Circuits, 2018)

11.4 A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links. - Zhaowen Wang; Yudong Zhang 006; Yuka Onizuka; Peter R. Kinget (ISSCC, 2021)

Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL. - Zhaowen Wang; Yudong Zhang 006; Yuka Onizuka; Peter R. Kinget (IEEE J. Solid State Circuits, 2022)

Analysis of Injection-Locked Ring Oscillators for Quadrature Clock Generation in Wireline or Optical Transceivers. - Yudong Zhang 006; Zhaowen Wang; Peter R. Kinget (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)