A multi-GHz area-efficient comparator with dynamic offset cancellation. - Lingkai Kong; Yue Lu 007; Elad Alon (CICC, 2011)

A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS. - Yue Lu 007; Kwangmo Jung; Yasuo Hidaka; Elad Alon (CICC, 2012)

BAG: a designer-oriented integrated framework for the development of AMS circuit generators. - John Crossley; Alberto Puggelli; Hanh-Phuc Le; B. Yang; R. Nancollas; Kwangmo Jung; Lingkai Kong; Nathan Narevsky; Yue Lu 007; Nicholas Sutardja; E. J. An; Alberto L. Sangiovanni-Vincentelli; et al. (ICCAD, 2013)

A 66Gb/s 46mW 3-tap decision-feedback equalizer in 65nm CMOS. - Yue Lu 007; Elad Alon (ISSCC, 2013)

Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS. - Yue Lu 007; Elad Alon (IEEE J. Solid State Circuits, 2013)

Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters. - Yue Lu 007; Kwangmo Jung; Yasuo Hidaka; Elad Alon (IEEE J. Solid State Circuits, 2013)

A 60Gb/s 173mW receiver frontend in 65nm CMOS technology. - Jaeduk Han; Yue Lu 007; Nicholas Sutardja; Kwangmo Jung; Elad Alon (VLSIC, 2015)

Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology. - Jaeduk Han; Yue Lu 007; Nicholas Sutardja; Kwangmo Jung; Elad Alon (IEEE J. Solid State Circuits, 2016)

6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology. - Jaeduk Han; Yue Lu 007; Nicholas Sutardja; Elad Alon (ISSCC, 2017)

Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology. - Jaeduk Han; Nicholas Sutardja; Yue Lu 007; Elad Alon (IEEE J. Solid State Circuits, 2017)