A Stepped-RAM Reading and Multiplierless VLSI Architecture for Intra Prediction in HEVC. - Wei Zhou 020; Yue Niu 001; Xiaocong Lian; Xin Zhou 001; Jiamin Yang (PCM (1), 2016)

A 200MHZ 202.4GFLOPS@10.8W VGG16 accelerator in Xilinx VX690T. - Chunsheng Mei; Zhenyu Liu 001; Yue Niu 001; Xiangyang Ji; Wei Zhou 020; Dongsheng Wang 002 (GlobalSIP, 2017)

Sensitivity-based acceleration and compression algorithm for convolution neural network. - Yue Niu 001; Zhenyu Liu 001; Chunsheng Mei; Xiangyang Ji; Wei Zhou 020; Dongsheng Wang 002 (GlobalSIP, 2017)

SPEC2: SPECtral SParsE CNN Accelerator on FPGAs. - Yue Niu 001; Hanqing Zeng; Ajitesh Srivastava; Kartik Lakhotia; Rajgopal Kannan; Yanzhi Wang; Viktor K. Prasanna (HiPC, 2019)

Sensitivity-Oriented Layer-Wise Acceleration and Compression for Convolutional Neural Network. - Wei Zhou 020; Yue Niu 001; Guanwen Zhang (IEEE Access, 2019)

Reuse Kernels or Activations?: A Flexible Dataflow for Low-latency Spectral CNN Acceleration. - Yue Niu 001; Rajgopal Kannan; Ajitesh Srivastava; Viktor K. Prasanna (FPGA, 2020)