Metrology for analog module testing using analog testability bus. - Chauchin Su; Yue-Tsang Chen; Shyh-Jye Jou; Yuan-Tzu Ting (ICCAD, 1996)

Analog signal metrology for mixed signal ICs. - Chauchin Su; Yi-Ren Cheng; Yue-Tsang Chen; Shing Tenchen (Asian Test Symposium, 1997)

Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. - Chauchin Su; Yue-Tsang Chen; Shyh-Jye Jou (ITC, 1997)

Analog Module Metrology Using MNABST-1 P1149.4 Test Chip. - Yue-Tsang Chen; Chauchin Su (Asian Test Symposium, 1998)

Boundary scan BIST methodology for reconfigurable systems. - Chauchin Su; Shung-Won Jeng; Yue-Tsang Chen (ITC, 1998)

Analog Metrology and Stimulus Selection in a Noisy Environment. - Chauchin Su; Yue-Tsang Chen; Chung-Len Lee 001 (Asian Test Symposium, 1999)

All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. - Chauchin Su; Yue-Tsang Chen; Mu-Jeng Huang; Gen-Nan Chen; Chung-Len Lee 001 (DATE, 2000)

Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. - Chauchin Su; Yue-Tsang Chen (VTS, 2000)

Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis. - Chauchin Su; Yue-Tsang Chen; Shenshung Chiang (J. Inf. Sci. Eng., 2000)

Intrinsic response extraction for the removal of the parasiticeffects in analog test buses. - Chauchin Su; Yue-Tsang Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. - Yue-Tsang Chen; Chauchin Su (VTS, 2001)

Intrinsic response for analog module testing using an analog testability bus. - Chauchin Su; Yue-Tsang Chen; Shyh-Jye Jou (ACM Trans. Design Autom. Electr. Syst., 2001)