Approximate Adder with Hybrid Prediction and Error Compensation Technique. - Xinghua Yang; Yue Xing 001; Fei Qiao; Qi Wei 001; Huazhong Yang (ISVLSI, 2016)

Multistage Latency Adders Architecture Employing Approximate Computing. - Xinghua Yang; Yue Xing 001; Fei Qiao; Huazhong Yang (J. Circuits Syst. Comput., 2017)

A formal instruction-level GPU model for scalable verification. - Yue Xing 001; Bo-Yuan Huang 001; Aarti Gupta; Sharad Malik (ICCAD, 2018)

Leveraging Processor Modeling and Verification for General Hardware Modules. - Yue Xing 001; Huaixi Lu; Aarti Gupta; Sharad Malik (DATE, 2021)

Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models. - Yue Xing 001; Aarti Gupta; Sharad Malik (ASP-DAC, 2022)

Compositional Verification Using a Formal Component and Interface Specification. - Yue Xing 001; Huaixi Lu; Aarti Gupta; Sharad Malik (ICCAD, 2022)

SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications. - Huaixi Lu; Yue Xing 001; Aarti Gupta; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2023)

Hierarchical Formal Verification of Hardware. - Huaixi Lu; Yue Xing 001; Aarti Gupta; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)