The first MAJC microprocessor: a dual CPU system-on-a-chip. - Andre Kowalczyk; Victor Adler; Chaim Amir; Frank Chiu; Choon Ping Chng; Willem J. de Lange; Yuefei Ge; Subhendra Ghosh; Tan Canh Hoang; Baoqing Huang; Shree Kant; Y. S. Kao; et al. (IEEE J. Solid State Circuits, 2001)

Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor. - Georgios K. Konstadinidis; Mamun Rashid; Peter F. Lai; Yukio Otaguro; Yannis Orginos; Sudhendra Parampalli; Mark Steigerwald; Shriram Gundala; Rambabu Pyapali; Leonard Rarick; Ilyas Elkin; Yuefei Ge; et al. (ISSCC, 2008)

Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor. - Georgios K. Konstadinidis; Marc Tremblay; Shailender Chaudhry; Mamun Rashid; Peter F. Lai; Yukio Otaguro; Yannis Orginos; Sudhendra Parampalli; Mark Steigerwald; Shriram Gundala; Rambabu Pyapali; Leonard Rarick; et al. (IEEE J. Solid State Circuits, 2009)

3.6GHz 16-core SPARC SoC processor in 28nm. - Jason Hart; Steve Butler; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Lance Kwong; Robert P. Masleid; et al. (ISSCC, 2013)

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. - Jason Hart; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Venkatram Krishnaswamy; Lance Kwong; Robert P. Masleid; et al. (IEEE J. Solid State Circuits, 2014)