Bad Data Identification Based on Optimized Local Outlier Detection Algorithm. - Jingxian Qi; Yuefeng Cao; Jianhua Shi (GRMSE (1), 2016)

A proved dither-injection method for memory effect in double sampling pipelined ADC. - Fubiao Cao; Yongzhen Chen; Yuefeng Cao; Fan Ye 001; Junyan Ren (ASICON, 2017)

An improved ring amplifier with process- and supply voltage-insensitive dead-zone. - Yuefeng Cao; Yongzhen Chen; Tianli Zhang; Fan Ye 001; Junyan Ren (MWSCAS, 2017)

An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. - Yuefeng Cao; Yongzhen Chen; Zhekan Ni; Fan Ye 001; Junyan Ren (APCCAS, 2018)

An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. - Yuefeng Cao; Tianli Zhang; Yongzhen Chen; Fan Ye 001; Junyan Ren (ISCAS, 2018)

A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. - Yongzhen Chen; Zhekan Ni; Yuefeng Cao; Fan Ye 001; Junyan Ren (ISCAS, 2018)

Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC. - Tianli Zhang; Yuefeng Cao; Fan Ye 001; Junyan Ren (ISCAS, 2018)

A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period. - Shumin Zhang; Yuefeng Cao; Fan Ye 001; Junyan Ren (ASICON, 2019)

Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. - Tianli Zhang; Yuefeng Cao; Shumin Zhang; Chixiao Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2019)

A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. - Yuefeng Cao; Shumin Zhang; Tianli Zhang; Yongzhen Chen; Yutong Zhao; Chixiao Chen; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT. - Xiang-Hui Pan; Buhui Rui; Yuefeng Cao; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2023)

A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors. - Minglei Zhang; Yuefeng Cao; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (VLSI Technology and Circuits, 2023)

The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs. - Chi-Hang Chan; Minglei Zhang; Yuefeng Cao; Honazhi Zhao; Rui Paulo Martins; Yan Zhu 001 (CICC, 2024)

22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2024)

A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2024)

A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2025)