A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS for Baseband Wireless Transmitter. - Yifei Wang; Xiaofei Wang; Yuekang Guo; Ting Jin (ASICON, 2019)

A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers. - Ran Wang; Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Naifeng Jing; Jianjun Zhou (ISCAS, 2020)

An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE Trans. Circuits Syst., 2020)

Analysis of SAR ADC Quantization Error and Nonlinearity in PMCW Automotive Radar. - Tao Zhong; Yuekang Guo; Jing Jin 005 (ASICON, 2021)

A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (ISCAS, 2021)

A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC. - Yuekang Guo; Jing Jin 005; Jianjun Zhou (MWSCAS, 2021)

A Center Frequency Calibration Technique for Ring VCO Exploiting Delay-1 Detection. - Yuekang Guo; Qiang Pan; Xiaoming Liu 008; Jing Jin 005 (MWSCAS, 2021)

A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs. - Yanlin He; Yuekang Guo; Jing Jin 005; Jianjun Zhou (MWSCAS, 2021)

A Linearization Technique for Ring VCO Exploiting Bulk-Modulation. - Qiang Pan; Yuekang Guo; Jing Jin 005; Jianjun Zhou (MWSCAS, 2021)

A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS. - Mengying Hu; Jing Jin 005; Yuekang Guo; Xiaoming Liu 008; Jianjun Zhou (Circuits Syst. Signal Process., 2021)

A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme. - Yuekang Guo; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou (ISCAS, 2022)

A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration. - Ke Wu; Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (MWSCAS, 2022)

A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique. - Ran Bu; Jing Jin 005; Zhaolin Yang; Yuekang Guo; Jianjun Zhou (Circuits Syst. Signal Process., 2022)

An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP. - Chao Yang; Xiaoming Liu 008; Jing Jin 005; Yuekang Guo; Jianjun Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{ text{VCO}}- text{Locked}- text{Loop}$. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Zhaolin Yang; Jianjun Zhou (ISCAS, 2023)

A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration. - Shunyan Wang; Yuekang Guo; Qiang Pan; Xiaoming Liu 008; Shan Wang; Jing Jin 005 (MWSCAS, 2023)

A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions. - Ke Wu; Yuekang Guo; Xiaoming Liu 008; Jing Jin 005; Howard C. Yang; Jianjun Zhou (MWSCAS, 2023)

A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE J. Solid State Circuits, 2023)

A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE J. Solid State Circuits, 2023)

A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer. - Jing Jin 005; Yuekang Guo; Meng Xu; Xiaoming Liu 008; Nan Sun; Jianjun Zhou (CICC, 2024)

A Self-Calibrated Sampling Noise Cancellation Technique for Noise-Shaping SAR ADC. - Zhengyuan Lou; Meng Xu; Yuekang Guo; Jing Jin 005; Jianjun Zhou (ISCAS, 2024)

A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers. - Xiaofei Wang; Jing Jin 005; Xiaoming Liu 008; Hui Wang 023; Huzhi Tang; Chao Yang; Yuekang Guo; Tingting Mo; Jianjun Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An EF-CIFF Noise-Shaping SAR ADC with A Joint Dynamic Amplifier, Comparator and Lossless Passive Summer Structure. - Yuzhi Ai; Yuekang Guo; Zhengyuan Lou; Hui Zhang; Jing Jin 005; Jianjun Zhou (ISCAS, 2025)

A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator. - Jinwei Wu; Yuekang Guo; Meng Xu; Lingyan Fan; Jing Jin 005; Jianjun Zhou (ISCAS, 2025)

A 14-bit 2.6GS/s RF sampling pipelined ADC in 28nm CMOS. - Hui Zhang; Dawei Dong; Haijun Wang; Dan Li; Yuan Gao; Chaoyi Hu; Hao Xu; Xinlei Song; Jing Jin 005; Yuekang Guo; Lin Cheng (Microelectron. J., 2025)

A two-phase oscillation scheme with direct background correction for VCO-based ADC. - Tao Zhong; Yuekang Guo; Jing Jin 005; Jianjun Zhou (Microelectron. J., 2025)