Design SRAMs for burn-in. - William R. Reohr; Yuen H. Chan; Donald W. Plass; Antonio Pelella; Philip T. Wu (VTS, 1993)

High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor. - James D. Warnock; Leon J. Sigal; Brian W. Curran; Yuen H. Chan (ICCD, 1997)

Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. - Leon J. Sigal; James D. Warnock; Brian W. Curran; Yuen H. Chan; Peter J. Camporese; Mark D. Mayo; William V. Huott; Daniel R. Knebel; Ching-Te Chuang; James P. Eckhardt; Philip T. Wu (IBM J. Res. Dev., 1997)

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. - Charles F. Webb; Carl J. Anderson; Leon J. Sigal; Kenneth L. Shepard; John S. Liptay; James D. Warnock; Brian W. Curran; Barry Krumm; Mark D. Mayo; Peter J. Camporese; Eric M. Schwarz; Mark S. Farrell; et al. (IEEE J. Solid State Circuits, 1997)

Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor. - Dale E. Hoffman; Robert M. Averill III; Brian W. Curran; Yuen H. Chan; Allan H. Dansky; Robert F. Hatch; Timothy G. McNamara; Thomas J. McPherson; Gregory A. Northrop; Leon J. Sigal; Anthony Pelella; Patrick M. Williams (ICCD, 1998)

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA). - William V. Huott; Moyra K. McManus; Daniel R. Knebel; Steve Steen; Dennis Manzer; Pia N. Sanda; Steven C. Wilson; Yuen H. Chan; Antonio Pelella; Stanislav Polonsky (ITC, 1999)

IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology. - Brian W. Curran; Yuen H. Chan; Philip T. Wu; Peter J. Camporese; Gregory A. Northrop; Robert F. Hatch; Lisa B. Lacey; James P. Eckhardt; David T. Hui; Howard H. Smith (IBM J. Res. Dev., 2002)

Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. - Rajiv V. Joshi; Saibal Mukhopadhyay; Donald W. Plass; Yuen H. Chan; Ching-Te Chuang; Anirudh Devgan (ESSCIRC, 2004)

A novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI. - Rajiv V. Joshi; Yuen H. Chan (ESSCIRC, 2005)

A 8Kb domino read SRAM with hit logic and parity checker. - Antonio Pelella; Arthur Tuminaro; Ryan T. Freese; Yuen H. Chan (ESSCIRC, 2005)

An advanced optical diagnostic technique of IBM z990 eServer microprocessor. - Peilin Song; Franco Stellari; Bill Huott; Otto Wagner; Uma Srinivasan 002; Yuen H. Chan; Rick Rizzolo; H. J. Nam; James P. Eckhardt; Timothy G. McNamara; Ching-Lung Tong; Alan J. Weger; et al. (ITC, 2005)

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor. - Brian W. Curran; Bradley D. McCredie; Leonid Sigal; Eric M. Schwarz; Bruce M. Fleischer; Yuen H. Chan; D. Webber; Vaden Vaden; A. Goyal (ISSCC, 2006)

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. - John Davis; Don Plass; Paul Bunce; Yuen H. Chan; Antonio Pelella; Rajiv V. Joshi; A. Chen; William V. Huott; Thomas J. Knips; Pradip Patel; K. Lo; Eric Fluhr (ISSCC, 2006)

Design of the Power6 Microprocessor. - Joshua Friedrich; Bradley D. McCredie; Norman K. James; Bill Huott; Brian W. Curran; Eric Fluhr; Gaurav Mittal; Eddie Chan; Yuen H. Chan; Donald W. Plass; Sam G. Chu; Hung Q. Le; et al. (ISSCC, 2007)

IBM POWER6 SRAM arrays. - Donald W. Plass; Yuen H. Chan (IBM J. Res. Dev., 2007)

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. - Azeez J. Bhavnagarwala; Stephen Kosonocky; Carl Radens; Yuen H. Chan; Kevin Stawiasz; Uma Srinivasan 002; Steven P. Kowalczyk; Matthew M. Ziegler (IEEE J. Solid State Circuits, 2008)

Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. - Rajiv V. Joshi; Saibal Mukhopadhyay; Donald W. Plass; Yuen H. Chan; Ching-Te Chuang; Yue Tan (IEEE J. Solid State Circuits, 2009)

The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane. - Rajiv V. Joshi; Rouwaida Kanj; Anthony Pelella; Arthur Tuminaro; Yuen H. Chan (IEEE Des. Test Comput., 2010)

Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor. - Antonio Pelella; Yuen H. Chan; Bargav Balakrishnan; Pradip Patel; Daniel Rodko; Richard E. Serton (ISSCC, 2011)

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system. - James D. Warnock; Y. Chan; William V. Huott; Sean M. Carey; Michael F. Fee; Huajun Wen; Mary Jo Saccamango; Frank Malgioglio; Patrick J. Meaney; Donald W. Plass; Yuen H. Chan; Mark D. Mayo; et al. (ISSCC, 2011)

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. - James D. Warnock; Yiu-Hing Chan; Sean M. Carey; Huajun Wen; Patrick J. Meaney; Guenter Gerwig; Howard H. Smith; Yuen H. Chan; John Davis; Paul Bunce; Antonio Pelella; Daniel Rodko; et al. (IEEE J. Solid State Circuits, 2012)

7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor. - John Davis; Paul Bunce; Diana M. Henderson; Yuen H. Chan; Uma Srinivasan 002; Daniel Rodko; Pradip Patel; Thomas J. Knips; Tobias Werner 001 (ISSCC, 2013)

5.5GHz system z microprocessor and multi-chip module. - James D. Warnock; Yuen H. Chan; Hubert Harrer; David L. Rude; Ruchir Puri; Sean M. Carey; Gerard Salem; Guenter Mayer; Yiu-Hing Chan; Mark D. Mayo; Adam Jatkowski; Gerald Strevig; et al. (ISSCC, 2013)

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module. - James D. Warnock; Yuen H. Chan; Hubert Harrer; Sean M. Carey; Gerard Salem; Doug Malone; Ruchir Puri; Jeffrey A. Zitz; Adam Jatkowski; Gerald Strevig; Ayan Datta; Anne Gattiker; et al. (IEEE J. Solid State Circuits, 2014)

4.1 22nm Next-generation IBM System z microprocessor. - James D. Warnock; Brian W. Curran; John Badar; Gregory Fredeman; Donald W. Plass; Yuen H. Chan; Sean M. Carey; Gerard Salem; Friedrich Schroeder; Frank Malgioglio; Guenter Mayer; Christopher J. Berry; et al. (ISSCC, 2015)

IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors. - David Wolpert 001; Erwin Behnen; Leon J. Sigal; Yuen H. Chan; Gustavo Enrique Téllez; Douglas Bradley; Richard E. Serton; Rajesh Veerabhadraiah; William Ansley; Andrew Bianchi; Nagu Dhanwada; Sungjae Lee; et al. (IBM J. Res. Dev., 2018)