Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. - Fangyuan Dang; Yuan Wang 001; Yuequan Liu; Song Jia; Xing Zhang 002 (ASICON, 2015)

A reference-less all-digital burst-mode CDR with embedded TDC. - Mengyin Jiang; Yuan Wang 001; Baoguang Liu; Yuequan Liu; Song Jia; Xing Zhang 002 (ASICON, 2015)

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance. - Yuequan Liu; Yuan Wang 001; Song Jia; Xing Zhang 002 (ISCAS, 2015)

Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics. - Yuan Wang 001; Yuequan Liu; Mengyin Jiang; Song Jia; Xing Zhang 002 (ISCAS, 2016)

Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process. - Yuan Wang 001; Yuequan Liu; Song Jia; Xing Zhang 002 (Int. J. Circuit Theory Appl., 2017)