Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor. - Daniel W. Bliss; Tutu Ajayi; Ali Akoglu; Ilkin Aliyev; Toygun Basaklar; Leul Belayneh; David T. Blaauw; John S. Brunhaver; Chaitali Chakrabarti; Liangliang Chang; Kuan-Yu Chen 001; Ming-Hung Chen; et al. (ISCAS, 2022)

A Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar Decoding. - Yufan Yue; Tutu Ajayi; Xueyang Liu; Peiwen Xing; Zihan Wang; David T. Blaauw; Ronald G. Dreslinski; Hun-Seok Kim (ISLPED, 2022)

A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET. - Kuan-Yu Chen 001; Chi-Sheng Yang; Yu-Hsiu Sun; Chien-Wei Tseng; Morteza Fayazi; Xin He; Siying Feng; Yufan Yue; Trevor N. Mudge; Ronald G. Dreslinski; Hun-Seok Kim; David T. Blaauw (VLSI Technology and Circuits, 2022)

ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications. - Seungkyu Choi; Huanshihong Deng; Kuan-Yu Chen 001; Yufan Yue; David T. Blaauw; Hun-Seok Kim (ISLPED, 2024)

DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET. - Kuan-Yu Chen 001; Chi-Sheng Yang; Yu-Hsiu Sun; Chien-Wei Tseng; Morteza Fayazi; Xin He; Siying Feng; Yufan Yue; Trevor N. Mudge; Ronald G. Dreslinski; Hun-Seok Kim; David T. Blaauw (IEEE J. Solid State Circuits, 2025)