Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. - Yufei Ma 002; Minkyu Kim 001; Yu Cao 001; Jae-sun Seo; Sarma B. K. Vrudhula (ICCD, 2015)

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. - Naveen Suda; Vikas Chandra; Ganesh Dasika; Abinash Mohanty; Yufei Ma 002; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001 (FPGA, 2016)

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. - Yufei Ma 002; Naveen Suda; Yu Cao 001; Jae-sun Seo; Sarma B. K. Vrudhula (FPL, 2016)

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (FPGA, 2017)

An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (FPL, 2017)

End-to-end scalable FPGA accelerator for deep residual networks. - Yufei Ma 002; Minkyu Kim 001; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (ISCAS, 2017)

Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. - Yufei Ma 002; Tu Zheng; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (ICCAD, 2018)

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. - Yufei Ma 002; Naveen Suda; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (Integr., 2018)

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Hardware Acceleration of Deep Convolutional Neural Networks on FPGA. - Yufei Ma 002 (2018)

Automatic Compiler Based FPGA Accelerator for CNN Training. - Shreyas Kolala Venkataramanaiah; Yufei Ma 002; Shihui Yin; Eriko Nurvitadhi; Aravind Dasu; Yu Cao 001; Jae-sun Seo (FPL, 2019)

Efficient Network Construction Through Structural Plasticity. - Xiaocong Du; Zheng Li 020; Yufei Ma 002; Yu Cao 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference. - Jiayu Wen; Yufei Ma 002; Zhongfeng Wang 001 (APCCAS, 2020)

In-Memory Computing: The Next-Generation AI Computing Paradigm. - Yufei Ma 002; Yuan Du; Li Du; Jun Lin 001; Zhongfeng Wang 001 (ACM Great Lakes Symposium on VLSI, 2020)

Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks. - Zhiyuan Chen 009; Yufei Ma 002; Zhongfeng Wang 001 (ICCAD, 2020)

Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA. - Hui Zhang; Wei Wu; Yufei Ma 002; Zhongfeng Wang 001 (ISVLSI, 2020)

Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA. - Xiao Wu; Yufei Ma 002; Zhongfeng Wang 001 (SoCC, 2020)

Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-Sun Seo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Performance Modeling for CNN Inference Accelerators on FPGA. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-Sun Seo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. - Yufei Ma 002; Gokul Krishnan; Yu Cao 001; Le Ye; Ru Huang 001 (FPGA, 2021)

DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks. - Yikan Qiu; Yufei Ma 002; Wentao Zhao; Meng Wu 005; Le Ye; Ru Huang 001 (ICCAD, 2022)

Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs. - Zhiyuan Chen 009; Yufei Ma 002; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs. - Xiao Wu; Yufei Ma 002; Meiqi Wang; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation. - Peiyu Chen; Meng Wu 005; Yufei Ma 002; Le Ye; Ru Huang 001 (ASP-DAC, 2023)

A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. - Ying Liu; Zhiyuan Chen 009; Zhixuan Wang; Wentao Zhao; Wei He; Jianfeng Zhu; Oijun Wang; Ning Zhang; Tianyu Jia; Yufei Ma 002; Le Ye; Ru Huang 001 (CICC, 2023)

A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware. - Yanchi Dong; Tianyu Jia; Kaixuan Du; Yiqi Jing; Qijun Wang; Pixian Zhan; Yadong Zhang; Fengyun Yan; Yufei Ma 002; Yun Liang 001; Le Ye; Ru Huang 001 (DAC, 2023)

DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler. - Yiqi Jing; Yiyang Sun; Xiao Wang; Wentao Zhao; Meng Wu 005; Fengyun Yan; Yufei Ma 002; Le Ye; Tianyu Jia (ISLPED, 2023)

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. - Peiyu Chen; Meng Wu 005; Wentao Zhao; Jiajia Cui; Zhixuan Wang; Yadong Zhang; Qijun Wang; Jiayoon Ru; Linxiao Shen; Tianyu Jia; Yufei Ma 002; Le Ye; et al. (ISSCC, 2023)

An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. - Ying Liu; Yufei Ma 002; Wei He; Zhixuan Wang; Linxiao Shen; Jiayoon Ru; Ru Huang 001; Le Ye (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Research progress on low-power artificial intelligence of things (AIoT) chip design. - Le Ye; Zhixuan Wang; Tianyu Jia; Yufei Ma 002; Linxiao Shen; Yihan Zhang 002; Heyi Li; Peiyu Chen; Meng Wu 005; Ying Liu; Yiqi Jing; Hao Zhang 119; et al. (Sci. China Inf. Sci., 2023)

Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow. - Yikan Qiu; Yufei Ma 002; Meng Wu 005; Yifan Jia 009; Xinyu Qu; Zecheng Zhou; Jincheng Lou; Tianyu Jia; Le Ye; Ru Huang 001 (CICC, 2024)

S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications. - Meng Wu 005; Wenjie Ren; Peiyu Chen; Wentao Zhao; Yiqi Jing; Jiayoon Ru; Zhixuan Wang; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (CICC, 2024)

An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. - Zhiyuan Chen 009; Yufei Ma 002; Keyi Li; Yifan Jia 009; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (DAC, 2024)

AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. - Yiqi Jing; Meng Wu 005; Jiaqi Zhou; Yiyang Sun; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (DAC, 2024)

30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing. - Ying Liu; Yufei Ma 002; Ninghui Shang; Tianhao Zhao; Peiyu Chen; Meng Wu 005; Jiayoon Ru; Tianyu Jia; Le Ye; Zhixuan Wang; Ru Huang 001 (ISSCC, 2024)

A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup. - Yanchi Dong; Xueping Liu; Kangbo Bai; Guoxiang Li; Meng Wu 005; Yiqi Jing; Yihan Zhang 002; Pixian Zhan; Yadong Zhang; Yufei Ma 002; Ru Huang 001; Le Ye; et al. (VLSI Technology and Circuits, 2024)

Alternating Subspace Approximate Message Passing. - Xu Zhu; Yufei Ma 002; Xiaoguang Li; Tiejun Li (CoRR, 2024)

Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network. - Ying Liu; Zhiyuan Chen 009; Wentao Zhao; Tianhao Zhao; Tianyu Jia; Zhixuan Wang; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. - Yufei Ma 002; Yikan Qiu; Wentao Zhao; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Accelerating Diffusion Transformer via Increment-Calibrated Caching with Channel-Aware Singular Value Decomposition. - Zhiyuan Chen 009; Keyi Li; Yifan Jia 009; Le Ye; Yufei Ma 002 (CVPR, 2025)

13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction. - Ying Liu; Jie Li; Qining Zhang; Tianhao Zhao; Chenhao Shi; Ninghui Shang; Peiyu Chen; Xiaohuan Ge; Yufei Ma 002; Linxiao Shen; Zhixuan Wang; Ru Huang 001; et al. (ISSCC, 2025)

A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing. - Peiyu Chen; Wentao Zhao; Meng Wu 005; Linxiao Shen; Tianyu Jia; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE J. Solid State Circuits, 2025)