A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. - Ji Zhang 001; Yiqing Ding; Xiaoyong Xue; Gang Jin; Yuxin Wu; Yufeng Xie 001; Yinyin Lin (IEICE Trans. Electron., 2010)

Novel RRAM programming technology for instant-on and high-security FPGAs. - Xiaoyong Xue; Wenxiang Jian; Yufeng Xie 001; Qing Dong; Rui Yuan; Yinyin Lin (ASICON, 2011)

A BIST scheme for high-speed Gain Cell eDRAM. - Bing Yan; Yufeng Xie 001; Rui Yuan; Yinyin Lin (ASICON, 2011)

Novel 2T programmable element to improve density and performance of FPGA. - Xiaoyong Xue; Yufeng Xie 001; Yinyin Lin (IEICE Electron. Express, 2011)

64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. - Yufeng Xie 001; Wenxiang Jian; Xiaoyong Xue; Gang Jin; Yinyin Lin (IEICE Electron. Express, 2012)

A 0.13 µm 8 Mb Logic-Based Cux Siy O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction. - Xiaoyong Xue; Wenxiang Jian; Jianguo Yang; Fanjie Xiao; Gang Chen; Shuliu Xu; Yufeng Xie 001; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEEE J. Solid State Circuits, 2013)

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. - Yufeng Xie 001; Xiaoyong Xue; Jianguo Yang; Yinyin Lin; Qingtian Zou; Ryan Huang; Jingang Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. - Xiaoyong Xue; Yarong Fu; Yanqing Zhao; Juan Xu; Jianguo Yang; Yufeng Xie 001; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme. - Danqing Wu; Shilin Yan; Haodi Tang; Yu Wang; Jiayun Feng; Xianwu Hu; Jiaxin Cao; Yufeng Xie 001 (ASICON, 2019)

An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process. - Xianwu Hu; Dongyang Li; Yu Wang; Jiayun Feng; Zizhao Ma; Shaohao Wang; Tai Min; Xiaoyang Zeng; Yufeng Xie 001 (ASICON, 2021)

A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight. - Yukai Lin; Yu Wang; Xianwu Hu; Jiayun Feng; Gan Wen; Xiankui Xiong; Haidong Tian; Yufeng Xie 001 (ASICON, 2021)

A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process. - Xianwu Hu; Yu Wang; Jiayun Feng; Zizhao Ma; Xiaoyang Zeng; Yufeng Xie 001 (ISCAS, 2022)

GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications. - Zizhao Ma; Xianwu Hu; Gan Wen; Yihao Wang; Zeming Wang; Yukai Lin; Yu Wang; Yuhao Guo; Yanlei Li; Xingdong Liang; Xiaoyang Zeng; Yufeng Xie 001 (A-SSCC, 2023)

A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation. - Zizhao Ma; Xianwu Hu; Yihao Wang; Gan Wen; Xiaoyang Zeng; Yufeng Xie 001 (ISCAS, 2023)

An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication. - Xianwu Hu; Yu Wang; Zizhao Ma; Gan Wen; Zeming Wang; Zhichao Lu; Yunlong Liu; Yanlei Li; Xingdong Liang; Xiaoyang Zeng; Yufeng Xie 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Contactless Diagnosis Method and Unsupervised Learning for Panel-Level Photovoltaic Plant Operation and Maintenance. - Yifan Wang; Jianrong Xu; Fei Xu; Long Deng; Chensheng Jin; Wenzhong Bao; Yufeng Xie 001 (IEEE Access, 2024)

A 40nm STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration. - Hongrui Meng; Yajun Wu; Shengchao Zhou; Zizhao Ma; Tai Min; Shaohao Wang; Yufeng Xie 001 (ISCAS, 2025)

High sensing margin and parallelism 6T-2MTJ SOT-MRAM based TCAM for energy-Efficient Similarity Priority calculation in MANNs. - Shengchao Zhou; Teng Zou; Zeming Wang; Xianwu Hu; Hongrui Meng; Yajun Wu; Chuxin Zhang; Caihua Wan; Yufeng Xie 001 (ISCAS, 2025)

Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage. - Chunshan Wang; Zizhao Ma; Yuxuan Zhu; Chensheng Jin; Dongyu Chen; Chuxin Zhang; Yining Chen; Wenzhong Bao; Yufeng Xie 001 (IEEE Access, 2025)