Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop. - Yugal Kishore Maheshwari; Kleber Stangherlin; Derek Wright; Manoj Sachdev (ICECS, 2021)

A power-efficient, single-phase, contention-free flip-flop with only three clock transistors. - Yugal Kishore Maheshwari; Manoj Sachdev (Microelectron. J., 2024)

Low-Power, Low-Energy, Static, Contention-Free, TSPC Dual-Edge Triggered Flip-Flops. - Yugal Kishore Maheshwari; Manoj Sachdev (IEEE Access, 2025)

VLFF - A very low-power flip-flop with only two clock transistors. - Yugal Kishore Maheshwari; Manoj Sachdev (Integr., 2025)