VLSI on-chip interconnection performance simulations and measurements. - Daniel C. Edelstein; George A. Sai-Halasz; Yuh-Jier Mii (IBM J. Res. Dev., 1995)

CMOS scaling into the 21st century: 0.1 µm and beyond. - Yuan Taur; Yuh-Jier Mii; David J. Frank; H.-S. Philip Wong; Douglas A. Buchanan; Shalom J. Wind; Stephen A. Rishton; Watson A. Sai-Halasz; Edward J. Nowak (IBM J. Res. Dev., 1995)

28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications. - S. H. Yang; J. Y. Sheu; M. K. Ieong; M. H. Chiang; T. Yamamoto; J. J. Liaw; S. S. Chang; Y. M. Lin; T. L. Hsu; J. R. Hwang; J. K. Ting; C. H. Wu; et al. (CICC, 2011)

Semiconductor Innovations, from Device to System. - Yuh-Jier Mii (VLSI Technology and Circuits, 2022)