Synchronization of chaotic neural networks with time delay in the leakage term and parametric uncertainties based on sampled-data control. - Qintao Gan; Yuhua Liang (J. Frankl. Inst., 2012)

Synchronization of Non-Identical Unknown Chaotic Delayed Neural Networks Based on Adaptive Sliding Mode Control. - Qintao Gan; Yuhua Liang (Neural Process. Lett., 2012)

Ultra-low energy switching scheme for SAR ADC. - Ruixue Ding; Qinglong Wu; Yuhua Liang; Zhangming Zhu (IEICE Electron. Express, 2015)

Strategy for SAR ADC with 87.5% area saving and 99.4% switching energy reduction over conventional approach. - Yuhua Liang; Zhangming Zhu; Jian Liu; Ruixue Ding (IEICE Electron. Express, 2015)

A Gain-Tunable Output Buffer for Audio-DAC with Common-Mode Output Independent of Gain Variation. - Yuhua Liang; Zhangming Zhu (J. Circuits Syst. Comput., 2015)

Calibration algorithm for 16-bit voltage-mode R-2R DAC. - Yuhua Liang; Zhangming Zhu; Ruixue Ding (Microelectron. J., 2015)

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS. - Yuhua Liang; Zhangming Zhu; Ruixue Ding (Microelectron. J., 2015)

A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- μm CMOS for Medical Implant Devices. - Zhangming Zhu; Yuhua Liang (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 0.6 V 31 nW 25 ppm/°C MOSFET-only sub-threshold voltage reference. - Yuhua Liang; Zhangming Zhu (Microelectron. J., 2017)

An Energy-Efficient Switching Scheme for Low-Power SAR ADC Design. - Yuhua Liang; Zhangming Zhu (J. Circuits Syst. Comput., 2018)

Analysis and Modeling of a SAR-VCO Hybrid ADC Architecture. - Yuhua Liang; Zhangming Zhu (J. Circuits Syst. Comput., 2018)

A 42ppm/∘C 0.7V 47nW Low-Complexity All-MOSFET Sub-Threshold Voltage Reference. - Yuhua Liang; Zhangming Zhu (J. Circuits Syst. Comput., 2018)

A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS. - Yuhua Liang; Zhangming Zhu (Microelectron. J., 2018)

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm CMOS. - Yi Xie; Yuhua Liang; Maliang Liu; Shubin Liu; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances. - Yuhua Liang; Zhangming Zhu; Xueqing Li 002; Sumeet Kumar Gupta; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Enhanced CEST MRI Using the Residual of Inversed Z-Spectra for Ischemia Detection. - Lihong Zhang; Yuhua Liang; Yanrong Chen; Guangzu Li; Mengbei Zhang; Yingcheng Zhao; Xiaoli Wang; Xiaolei Song (IEEE Access, 2020)

A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs. - Dengquan Li; Maliang Liu; Shubin Liu; Yuhua Liang; Ruixue Ding (Microelectron. J., 2021)

A 5 MHz-BW 71.7-dB SNDR two-step hybrid-domain ADC in 65-nm CMOS. - Zhe Yu; Yuhua Liang; Shubin Liu (Microelectron. J., 2021)

Radio frequency analog-to-digital converters: Systems and circuits review. - Dengquan Li; Xin Zhao 035; Shubin Liu; Maliang Liu; Ruixue Ding; Yuhua Liang; Zhangming Zhu (Microelectron. J., 2022)

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems. - Yuhua Liang; Changying Li; Shubin Liu; Zhangming Zhu (IEEE Trans. Biomed. Circuits Syst., 2022)

A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs. - Depeng Sun; Ruixue Ding; Feng Bu; Hongzhi Liang; Dengquan Li; Yuhua Liang; Shubin Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure. - Pinyun Yi; Yuhua Liang; Shubin Liu; Nuo Xu; Liang Fang; Yue Hao (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An energy-efficient switching scheme based on a splitting structure. - Juntao Cao; Yuhua Liang (Microelectron. J., 2023)

A reconfigurable 8-to-12-b 10-MS/s energy-efficient two-step ADC. - Xin Li; Yuhua Liang (Microelectron. J., 2023)

LMS-based digital background mismatch calibration technique for SAR ADC. - Jing Wan; Shida Song; Yuhua Liang (Microelectron. J., 2023)

A 99.93% energy-efficient switching scheme for SAR ADC without switching energy in the first three MSBs. - Zhe Yu; Yuhua Liang (Microelectron. J., 2023)

A configurable area-efficient LCoS chip design with centrosymmetric pixel array. - Tianhu Zhao; Yuhua Liang; Lichen Feng (Microelectron. J., 2023)

A Reconfigurable 12-to-18-Bit Dynamic Zoom ADC With Pole-Optimized Technique. - Yuhua Liang; Jinyu Ren; Li Chen; Haotian Lan; Jiajun Song; Shida Song; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells. - Zhe Yu; Yuhua Liang; Haotian Lan; Li Chen; Jiajun Song; Shida Song; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 0.64mm2Sensor Size, 32.5μg/√Hz Noise Floor, High Efficiency MEMS Capacitive Accelerometer Using High-Voltage Pulse Excitation Technique. - Longjie Zhong; Pengpeng Shang; Shubin Liu; Wenfei Cao; Lichen Feng; Yuhua Liang; Zhangming Zhu (CICC, 2024)

A 10-kHz 12-16-bit reconfigurable zoom ADC with pole optimization technique and floating current-starved amplifier. - Zhangming Zhu; Jiajun Song; Yuhua Liang (Sci. China Inf. Sci., 2024)

Analysis of non-ideal factors for a high precision interpolated resistor string DAC. - Li Chen; Yichen Duan; Yuhua Liang (Microelectron. J., 2024)

A 93.4-dB SNDR single-ended SAR ADC with a hybrid R-C DAC. - Haotian Lan; Yuhua Liang (Microelectron. J., 2024)

A 102.1-dB SNDR oversampling merge-mismatch-error-shaping SAR ADC in 180 nm CMOS. - Jinghong Xiao; Jiajun Song; Yuhua Liang (Microelectron. J., 2024)

A Less-Delay and Wide Conversion-Voltage-Range Level Shifter by Using Switched-Capacitor Technique for Power-Efficiency Health Electronics. - Quanzhen Duan; Tao Tao; Wuxiong Weng; Shengming Huang; Yuhua Liang; Jeongjin Roh; Xinpeng Xing (IEEE Trans. Consumer Electron., 2024)

A 16-bit 20KSPS SAR ADC with digital background calibration in 0.18 μm CMOS. - Xiaoyuan Miao; Yuhua Liang (Microelectron. J., 2025)

An 89-dB SNDR 50-kHz BW CT ZOOM ADC employing FIR DAC to enhance the ADC linearity. - Shida Song; Yuhua Liang (Microelectron. J., 2025)

A low-power 18-bit sigma-delta digital-to-analog converter with low-temperature-drift reference. - Xingyuan Tong; Hao Yu; Xin Xin; Yuhua Liang (Microelectron. J., 2025)

Algorithm of the inter-channel mismatches calibration in TIADC. - Chengjie Wang; Shengmin Yang; Yuhua Liang (Microelectron. J., 2025)

A 16 kHz-BW 93.1 dB-SNDR DT 2-1 MASH ΔΣ ADC With Cascading-CLS Technique for Accelerometer Measurement Applications. - Yuhua Liang; Ruiwen Liu; Zhangming Zhu (IEEE Trans. Instrum. Meas., 2025)

A 10kHz-BW 103.1-dB Max-SNDR Reconfigurable Zoom ADC With Noise-Shaping Effect Enhancement Technique for Biomedical Measurement. - Yuhua Liang; Jiajun Song; Zhangming Zhu (IEEE Trans. Instrum. Meas., 2025)

A 14-Bit 250-KS/s Calibration-Free SAR ADC for the Detection of Physiological Electrical Signals in Consumer Electronics. - Yuhua Liang; Ruiwen Liu; Yichen Duan; Zhangming Zhu (IEEE Trans. Consumer Electron., 2025)

An 8-to-12-Bit Resolution-Reconfigurable SAR ADC With Fast-Window-Switching Technique. - Yuhua Liang; Shida Song; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 20-kHz 106.1-dB SNDR Σ-Δ DAC Using FIA With Dynamic-Body-Biasing-Assisted CLS Technique. - Yuhua Liang; Yichen Duan; Zhangming Zhu (IEEE Trans. Consumer Electron., 2025)

A Peak-Injection CLS Technique for PVT-Robust Switched-Capacitor Amplifier. - Yuhua Liang; Pengkai Rui; Ruiwen Liu; Ruixue Ding; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)