A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator. - Suneui Park; Seyeon Yoo; Yuhwan Shin; Jeonghyun Lee; Jaehyouk Choi (ISSCC, 2022)

A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier. - Yongwoo Jo; Juyeop Kim; Yuhwan Shin; Chanwoong Hwang; Hangi Park; Jaehyouk Choi (ISSCC, 2023)

A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces. - Yuhwan Shin; Yongwoo Jo; Juyeop Kim; Junseok Lee; Jongwha Kim; Jaehyouk Choi (ISSCC, 2023)

A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68. - Suneui Park; Seyeon Yoo; Yuhwan Shin; Jeonghyun Lee; Jaehyouk Choi (IEEE J. Solid State Circuits, 2023)

A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier. - Yongwoo Jo; Juyeop Kim; Yuhwan Shin; Hangi Park; Chanwoong Hwang; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2023)

10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique. - Yuhwan Shin; Junseok Lee; Juyeop Kim; Yongwoo Jo; Jaehyouk Choi (ISSCC, 2024)

22.2: An 850µW 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces. - Jeongbeom Seo; Yoonseo Cho; Yuhwan Shin; Jaehyouk Choi (ISSCC, 2025)

A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces. - Yuhwan Shin; Yongwoo Jo; Juyeop Kim; Junseok Lee; Jongwha Kim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2025)