An Extremely Light-Weight Countermeasure to Power Analysis Attack in Dedicated Circuit for AES. - Yui Koyanagi; Tomoaki Ukezono (ISOCC, 2022)

A Cost-aware Generation Method of Disposable Random Value Exploiting Parallel S-box Implementation for Tamper-resistant AES Design. - Yui Koyanagi; Tomoaki Ukezono (CANDARW, 2023)

Reusing Outputs from S-Boxes for Tamper Resistant Design. - Tomoaki Ukezono; Yui Koyanagi (ICECET, 2023)

Effect of High Frequency Noise Using DCMs in FPGA on Power Analysis Attack. - Tomoaki Ukezono; Yui Koyanagi (ISCIT, 2023)

A Cost-Sensitive and Simple Masking Design for Side-Channels. - Yui Koyanagi; Tomoaki Ukezono (TENCON, 2023)

Random Clock Gating for Side-channel Protection. - Yui Koyanagi; Tomoaki Ukezono (APCCAS, 2024)

An OS Support for Tamper-Resistant Software Execution Using Empty Interruptions. - Soma Kato; Yui Koyanagi; Tomoaki Ukezono (ICISS, 2024)

A Light-weight and Tamper-resistant AES Implementation by FPGAs. - Yui Koyanagi; Tomoaki Ukezono; Toshinori Sato (ISCAS, 2024)

A Light-weight Random Number Generation for Tamper-resistant AES Circuit. - Tomoaki Ukezono; Yui Koyanagi (Int. J. Netw. Comput., 2024)