A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. - Yoshihisa Iwata; Kenji Tsuchida; Tsuneo Inaba; Yui Shimizu; R. Takizawa; Yoshihiro Ueda; Tadahiko Sugibayashi; Yoshiaki Asao; Takeshi Kajiyama; Keiji Hosotani; Sumio Ikegawa; Tadashi Kai; et al. (ISSCC, 2006)

MRAM Write Error Categorization with QCKB. - Yuui Shimizu; Hisanori Aikawa; Keiji Hosotani; Naoharu Shimomura; Tadashi Kai; Yoshihiro Ueda; Yoshiaki Asao; Yoshihisa Iwata; Kenji Tsuchida; Sumio Ikegawa (MTDT, 2006)

A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. - Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Kazuko Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; et al. (ISSCC, 2012)

A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface. - Kazushige Kanda; Noboru Shibata; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Naoaki Kanagawa; Yasuyuki Kajitani; Takeshi Ogawa; et al. (IEEE J. Solid State Circuits, 2013)

A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. - Hiroshi Maejima; Kazushige Kanda; Susumu Fujimura; Teruo Takagiwa; Susumu Ozawa; Jumpei Sato; Yoshihiko Shindo; Manabu Sato; Naoaki Kanagawa; Junji Musha; Satoshi Inoue; Katsuaki Sakurai; et al. (ISSCC, 2018)