Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs. - Yuichi Miyahara; Mitsuhiro Sano; Kazuo Koyama; Toshikazu Suzuki; Koichi Hamashita; Bang-Sup Song (ISSCC, 2013)

A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity. - Yuichi Miyahara; Mitsuhiro Sano; Kazuo Koyama; Toshikazu Suzuki; Koichi Hamashita; Bang-Sup Song (IEEE J. Solid State Circuits, 2014)

A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry. - Shota Konno; Yuichi Miyahara; Kazuki Sobue; Koichi Hamashita (A-SSCC, 2020)

A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting. - Manxin Li; Calvin Yoji Lee; Ahmed ElShater; Yuichi Miyahara; Kazuki Sobue; Koji Tomioka; Un-Ku Moon (ISSCC, 2023)

A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting. - Manxin Li; Calvin Yoji Lee; Praveen Kumar Venkatachala; Ahmed ElShater; Yuichi Miyahara; Kazuki Sobue; Koji Tomioka; Un-Ku Moon (IEEE J. Solid State Circuits, 2023)