A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix. - Yuichi Nakamura 002; Takeshi Yoshimura (DAC, 1995)

Multi-Level Logic Minimization Based on Multi-Signal Implications. - Masayuki Yuguchi; Yuichi Nakamura 002; Kazutoshi Wakabayashi; Tomoyuki Fujita (DAC, 1995)

A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface. - Yoshiyuki Ito; Yuichi Nakamura 002 (ASP-DAC, 1997)

Timing optimization by replacing flip-flops to latches. - Ko Yoshikawa; Yasuhiko Hagihara; Keisuke Kanamaru; Yuichi Nakamura 002; Shigeto Inui; Takeshi Yoshimura (ASP-DAC, 2004)

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. - Yuichi Nakamura 002; Kohei Hosokawa; Ichiro Kuroda; Ko Yoshikawa; Takeshi Yoshimura (DAC, 2004)

A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis. - Yuichi Nakamura 002; Takeshi Yoshimura (ISCAS (1), 2005)

An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs. - Yuichi Nakamura 002; Ko Yoshikawa; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Budgeting-free hierarchical design method for large scale and high-performance LSIs. - Yuichi Nakamura 002; Mitsuru Tagata; Takumi Okamoto; Shigeyoshi Tawada; Ko Yoshikawa (DAC, 2006)

A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Yoji Kajitani (FPT, 2006)

Fast FPGA-Emulation-Based Simulation Environment for Custom Processors. - Yuichi Nakamura 002; Kohei Hosokawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs. - Yuichi Nakamura 002; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Domino Logic Synthesis System and its Applications. - Ko Yoshikawa; Shigeto Inui; Yasuhiko Hagihara; Yuichi Nakamura 002; Takeshi Yoshimura (J. Circuits Syst. Comput., 2006)

Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs. - Kohei Hosokawa; Katsunori Tanaka; Yuichi Nakamura 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Yoji Kajitani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Relocation Method for Circuit Modifications. - Kunihiko Yanagibashi; Yasuhiro Takashima; Yuichi Nakamura 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A design method for skew tolerant latch design. - Yuichi Nakamura 002 (APCCAS, 2008)

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Atsushi Takahashi 001 (ISCAS, 2008)

Fine-Grained Power Gating Based on the Controlling Value of Logic Elements. - Lei Chen; Takashi Horiyama; Yuichi Nakamura 002; Shinji Kimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Post-Silicon Clock-Timing Tuning Based on Statistical Estimation. - Yuko Hashizume; Yasuhiro Takashima; Yuichi Nakamura 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition. - Liangwei Ge; Song Chen 001; Yuichi Nakamura 002; Takeshi Yoshimura (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools. - Katsunori Tanaka; Yuichi Nakamura 002; Atsushi Atarashi (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002 (FPL, 2009)

Delay analysis of sub-path on fabricated chips by several path-delay tests. - Takanobu Shiki; Yasuhiro Takashima; Yuichi Nakamura 002 (ISCAS, 2010)

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002 (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A low power technology mapping method for Adaptive Logic Module. - Wei Chen; Xiaolin Zhang; Takeshi Yoshimura; Yuichi Nakamura 002 (FPT, 2011)

Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology. - Sumio Morioka; Toshiyuki Isshiki; Satoshi Obana; Yuichi Nakamura 002; Kazue Sako (HOST, 2011)

A Verification and Analysis Tool Set for Embedded System Design. - Yuichi Nakamura 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip. - Hiroshi Saito; Tomohiro Yoneda; Yuichi Nakamura 002 (MCSoC, 2012)

Adaptive sensing of ECG signals using R-R interval prediction. - Shogo Nakaya; Yuichi Nakamura 002 (EMBC, 2013)

Revisiting rendezvous protocols in the context of RDMA-capable host channel adapters and many-core processors. - Masamichi Takagi; Yuichi Nakamura 002; Atsushi Hori; Balazs Gerofi; Yutaka Ishikawa (EuroMPI, 2013)

Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis. - Naoya Okada; Yuichi Nakamura 002; Shinji Kimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. - Shogo Nakaya; Makoto Miyamura; Noboru Sakimura; Yuichi Nakamura 002; Tadahiko Sugibayashi (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

An NoC-based evaluation platform for safety-critical automotive applications. - Tomohiro Yoneda; Masashi Imai; Hiroshi Saito; Takahiro Hanyu; Kenji Kise; Yuichi Nakamura 002 (APCCAS, 2014)

FPGA-accelerated complex event processing. - Takashi Takenaka; Hiroaki Inoue; Takeo Hosomi; Yuichi Nakamura 002 (VLSIC, 2015)

Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. - Masato Inagi; Yuichi Nakamura 002; Yasuhiro Takashima; Shin'ichi Wakabayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

PEVaS: Power and execution-time variation-aware scheduling for MPSoC. - Komei Nomura; Yasuhiro Takashima; Yuichi Nakamura 002 (NEWCAS, 2016)

Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations. - Peng Yang 003; Shigeru Nakamura; Kenichiro Yashiki; Zhehui Wang; Luan H. K. Duong; Zhifei Wang; Xuanqi Chen; Yuichi Nakamura 002; Jiang Xu 001 (NOCS, 2016)

Future trend of deep learning frameworks - From the perspective of big data analytics and HPC. - Takuya Araki; Yuichi Nakamura 002 (APSIPA, 2017)

Accelerating NFV application using CPU-FPGA tightly coupled architecture. - Yoshikazu Watanabe; Yuki Kobayashi; Takashi Takenaka; Takeo Hosomi; Yuichi Nakamura 002 (FPT, 2017)

Novel heterogeneous computing platforms and 5G communications for IoT applications. - Yuichi Nakamura 002; Hideyuki Shimonishi; Yuki Kobayashi; Kozo Satoda; Yashuhiro Matsunaga; Dai Kanetomo (ICCAD, 2017)

The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices. - Yuichi Nakamura 002 (ISPD, 2017)

Sustainable Incentive Mechanisms for Mobile Crowdsensing: Part 1. - Linghe Kong; Kui Ren 001; Muhammad Khurram Khan; Qi Li 002; Ammar Rayes; Mérouane Debbah; Yuichi Nakamura 002 (IEEE Commun. Mag., 2017)

Sustainable Incentive Mechanisms for Mobile Crowdsensing: Part 2. - Linghe Kong; Kui Ren 001; Muhammad Khurram Khan; Qi Li 002; Ammar Rayes; Mérouane Debbah; Yuichi Nakamura 002 (IEEE Commun. Mag., 2017)

A Loitering Discovery System Using Efficient Similarity Search Based on Similarity Hierarchy. - Jianquan Liu; Shoji Nishimura; Takuya Araki; Yuichi Nakamura 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Task Allocation and Scheduling Optimization in the Heterogeneous Core System. - Ryota Tsuchihashi; Komei Nomura; Yasuhiro Takashima; Yuichi Nakamura 002 (NGCAS, 2018)

Silicon Photonics for Computing Systems. - Jiang Xu 001; Yuichi Nakamura 002; Andrew B. Kahng (ACM J. Emerg. Technol. Comput. Syst., 2018)

Past, Current and Future Technologies for Optical Submarine Cables. - Hitoshi Takeshita; Masaki Sato; Yoshihisa Inada; Emmanuel Le Taillandier de Gabory; Yuichi Nakamura 002 (PHOTONICS@SC, 2019)

Theoretical and Experimental Analysis of Traveling Salesman Walk Problem. - Yasuhiro Takashima; Yuichi Nakamura 002 (APCCAS, 2021)

Can Quantum Technologies Change "Consumer Electronics"? - Yuichi Nakamura 002 (ICCE, 2021)

Technologies for Optical Submarine Cables: Past Present & Future. - Yuichi Nakamura 002; Hitoshi Takeshita (OFC, 2023)

The First Workshop on Quantum in Consumer Technology at IEEE Quantum Week 2022. - Rafael Sotelo 001; Jingbo Wang 001; Yuichi Nakamura 002; Ahmed Farouk; Rosario Arjona; Salvador E. Venegas-Andraca; Alex James 001; Araceli Venegas-Gomez; Bill Gonzalez (IEEE Consumer Electron. Mag., 2023)

The 2nd Workshop on Quantum in Consumer Technology At IEEE Quantum Week 2023. - Rafael Sotelo 001; Edoardo Giusto; Yuichi Nakamura 002; Jingbo Wang 001 (IEEE Consumer Electron. Mag., 2024)

The 3rd Workshop on Quantum in Consumer Technology at IEEE Quantum Week 2024. - Rafael Sotelo 001; Edoardo Giusto; Yuichi Nakamura 002; Jingbo Wang 001; Sreeraman Rajan; Himanshu Thapliyal (IEEE Consumer Electron. Mag., 2025)