A built-in test for functional testing in semiconductor random access memory. - Yukiya Miura; Hideo Tamamoto; Yuichi Narita (Syst. Comput. Jpn., 1987)

A built-in testing scheme for ic memories by considering address decoder and cell array separately. - Hideo Tamamoto; Hirotomo Sakusabe; Yuichi Narita (Syst. Comput. Jpn., 1987)

Built - in concurrent testing for semiconductor random access memories by concurrently testing cells on a word-line. - Yukiya Miura; Hideo Tamamoto; Yuichi Narita (Syst. Comput. Jpn., 1988)

Random current testing for CMOS logic circuits by monitoring a dynamic power supply current. - Hideo Tamamoto; Hiroshi Yokoyama; Yuichi Narita (EURO-DAC, 1992)

A Measuring System for Traffic Flow of Passers-by by Processing ITV Image in Real Time. - Hideo Tamamoto; Yuichi Narita; Akira Yanase; Futoshi Saito; Kazuto Komatsu (MVA, 1992)

Built-in current testing for CMOS logic circuits using random patterns. - Hiroshi Yokoyama; Hideo Tamamoto; Yuichi Narita (Syst. Comput. Jpn., 1994)

Integration of Medical Images into the Total Hospital Information System & Experiences at Kochi Medical School. - Yukio Kurihara; Yoshiyasu Okuhara; Yuichi Narita; Yasuhiro Kitazoe; Akihiro Sawada; Shoji Yoshida (HICSS, 1999)

Nursing Informatics Education based on the Text Type RDBMS and Its Effect. - Yuichi Narita; Yukiko Kikuchi; Yoshio Takemoto; Teruko Murakami; Yuziro Kurata (MedInfo, 2001)