% csauthors.net - beta - BibTeX bibliography of Yuichiro Ishii
@article{journals/ir/Tanaka-IshiiI07,
title = {Multilingual phrase-based concordance generation in real-time.},
year = {2007},
journal = {Inf. Retr.},
author = {{Kumiko Tanaka-Ishii} and {Yuichiro Ishii}}
}
@inproceedings{conf/cicc/TsukamotoKYINTTK11,
title = {Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs.},
year = {2011},
booktitle = {CICC},
author = {{Yasumasa Tsukamoto} and {Takeshi Kida} and {T. Yamaki} and {Yuichiro Ishii} and {Koji Nii} and {Koji Tanaka} and {Shinji Tanaka} and {Yuji Kihara}},
publisher = {IEEE},
booktitle = {2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011}
}
@article{journals/jssc/IshiiFTTNKY11,
title = {A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues.},
year = {2011},
journal = {IEEE J. Solid State Circuits},
author = {{Yuichiro Ishii} and {Hidehiro Fujiwara} and {Shinji Tanaka} and {Yasumasa Tsukamoto} and {Koji Nii} and {Yuji Kihara} and {Kazumasa Yanagisawa}}
}
@inproceedings{conf/ats/NiiTIYFO12,
title = {A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues.},
year = {2012},
booktitle = {Asian Test Symposium},
author = {{Koji Nii} and {Yasumasa Tsukamoto} and {Yuichiro Ishii} and {Makoto Yabuuchi} and {Hidehiro Fujiwara} and {Kazuyoshi Okamoto}},
publisher = {IEEE Computer Society},
booktitle = {21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012}
}
@inproceedings{conf/isscc/IshiiTNFYTTS12,
title = {A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs.},
year = {2012},
booktitle = {ISSCC},
author = {{Yuichiro Ishii} and {Yasumasa Tsukamoto} and {Koji Nii} and {Hidehiro Fujiwara} and {Makoto Yabuuchi} and {Koji Tanaka} and {Shinji Tanaka} and {Yasuhisa Shimazaki}},
publisher = {IEEE},
booktitle = {2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012}
}
@inproceedings{conf/isqed/NiiYFTIMM13,
title = {A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53\% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.},
year = {2013},
booktitle = {ISQED},
author = {{Koji Nii} and {Makoto Yabuuchi} and {Hidehiro Fujiwara} and {Yasumasa Tsukamoto} and {Yuichiro Ishii} and {Tetsuya Matsumura} and {Yoshio Matsuda}},
publisher = {IEEE},
booktitle = {International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013}
}
@inproceedings{conf/asscc/YokoyamaITFTMAM14,
title = {40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues.},
year = {2014},
booktitle = {A-SSCC},
author = {{Yoshisato Yokoyama} and {Yuichiro Ishii} and {Koji Tanaka} and {Tatsuya Fukuda} and {Yoshiki Tsujihashi} and {Atsushi Miyanishi} and {Shinobu Asayama} and {Keiichi Maekawa} and {Kazutoshi Shiba} and {Koji Nii}},
publisher = {IEEE},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014}
}
@inproceedings{conf/isqed/YokoyamaIKMTASTFNY14,
title = {40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU.},
year = {2014},
booktitle = {ISQED},
author = {{Yoshisato Yokoyama} and {Yuichiro Ishii} and {Hidemitsu Kojima} and {Atsushi Miyanishi} and {Yoshiki Tsujihashi} and {Shinobu Asayama} and {Kazutoshi Shiba} and {Koji Tanaka} and {Tatsuya Fukuda} and {Koji Nii} and {Kazumasa Yanagisawa}},
publisher = {IEEE},
booktitle = {Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014}
}
@inproceedings{conf/vlsic/TanakaIYSTTNS14,
title = {A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.},
year = {2014},
booktitle = {VLSIC},
author = {{Shinji Tanaka} and {Yuichiro Ishii} and {Makoto Yabuuchi} and {Toshiaki Sano} and {Koji Tanaka} and {Yasumasa Tsukamoto} and {Koji Nii} and {Hirotoshi Sato}},
publisher = {IEEE},
booktitle = {Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014}
}
@inproceedings{conf/asscc/YokoyamaIITTTN15,
title = {A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.},
year = {2015},
booktitle = {A-SSCC},
author = {{Yoshisato Yokoyama} and {Yuichiro Ishii} and {Toshihiro Inada} and {Koji Tanaka} and {Miki Tanaka} and {Yoshiki Tsujihashi} and {Koji Nii}},
publisher = {IEEE},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015}
}
@inproceedings{conf/asscc/IshiiYSMTYSSTN16,
title = {A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.},
year = {2016},
booktitle = {A-SSCC},
author = {{Yuichiro Ishii} and {Makoto Yabuuchi} and {Yohei Sawada} and {Masao Morimoto} and {Yasumasa Tsukamoto} and {Yuta Yoshida} and {Ken Shibata} and {Toshiaki Sano} and {Shinji Tanaka} and {Koji Nii}},
publisher = {IEEE},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016}
}
@inproceedings{conf/vlsic/YabuuchiSSITTN16,
title = {A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time.},
year = {2016},
booktitle = {VLSI Circuits},
author = {{Makoto Yabuuchi} and {Yohei Sawada} and {Toshiaki Sano} and {Yuichiro Ishii} and {Shinji Tanaka} and {Miki Tanaka} and {Koji Nii}},
publisher = {IEEE},
booktitle = {2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016}
}
@inproceedings{conf/asscc/YokoyamaION17,
title = {A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode.},
year = {2017},
booktitle = {A-SSCC},
author = {{Yoshisato Yokoyama} and {Yuichiro Ishii} and {Haruyuki Okuda} and {Koji Nii}},
publisher = {IEEE},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017}
}
@inproceedings{conf/asscc/YokoyamaMONINYI18,
title = {40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.},
year = {2018},
booktitle = {A-SSCC},
author = {{Yoshisato Yokoyama} and {Tomohiro Miura} and {Yukari Ouchi} and {Daisuke Nakamura} and {Jiro Ishikawa} and {Shunya Nagata} and {Makoto Yabuuchi} and {Yuichiro Ishii} and {Koji Nii}},
publisher = {IEEE},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018}
}
@inproceedings{conf/mhs/IshiiYKI18,
title = {Development of the experimental system that can acquire the gait data online in a quadruped robot.},
year = {2018},
booktitle = {MHS},
author = {{Yuichiro Ishii} and {Hiroki Yamamoto} and {Sungi Kim} and {Yusuke Ikemoto}},
publisher = {IEEE},
booktitle = {International Symposium on Micro-NanoMechatronics and Human Science, MHS 2018, Nagoya, Japan, December 9-12, 2018}
}
@inproceedings{conf/robio/YamamotoIKI18,
title = {Decomposition of Movement Data of Quadruped Robot by Using Autoencoder.},
year = {2018},
booktitle = {ROBIO},
author = {{Hiroki Yamamoto} and {Yuichiro Ishii} and {Sungi Kim} and {Yusuke Ikemoto}},
publisher = {IEEE},
booktitle = {IEEE International Conference on Robotics and Biomimetics, ROBIO 2018, Kuala Lumpur, Malaysia, December 12-15, 2018}
}
@inproceedings{conf/asscc/YokoyamaGMONINT19,
title = {A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.},
year = {2019},
booktitle = {A-SSCC},
author = {{Yoshisato Yokoyama} and {Kenji Goto} and {Tomohiro Miura} and {Yukari Ouchi} and {Daisuke Nakamura} and {Jiro Ishikawa} and {Shunya Nagata} and {Yoshiki Tsujihashi} and {Yuichiro Ishii}},
publisher = {IEEE},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macau, SAR, China, November 4-6, 2019}
}
@inproceedings{conf/vlsic/YokoyamaTTMYIT20,
title = {A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit.},
year = {2020},
booktitle = {VLSI Circuits},
author = {{Yoshisato Yokoyama} and {Miki Tanaka} and {Koji Tanaka} and {Masao Morimoto} and {Makoto Yabuuchi} and {Yuichiro Ishii} and {Shinji Tanaka}},
publisher = {IEEE},
booktitle = {IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020}
}
@article{journals/tvlsi/YokoyamaINK21,
title = {Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs.},
year = {2021},
journal = {IEEE Trans. Very Large Scale Integr. Syst.},
author = {{Yoshisato Yokoyama} and {Yuichiro Ishii} and {Koji Nii} and {Kazutoshi Kobayashi}}
}
@inproceedings{conf/vlsit/AoyagiYTIONNWHC23,
title = {A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.},
year = {2023},
booktitle = {VLSI Technology and Circuits},
author = {{Yumito Aoyagi} and {Makoto Yabuuchi} and {Tomotaka Tanaka} and {Yuichiro Ishii} and {Yoshiaki Osada} and {Takaaki Nakazato} and {Koji Nii} and {Isabel Wang} and {Yu-Hao Hsu} and {Hong-Chen Cheng} and {Hung-Jen Liao} and {Tsung-Yung Jonathan Chang}},
publisher = {IEEE},
booktitle = {2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023}
}
@article{journals/jssc/YokoyamaNITK23,
title = {Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing.},
year = {2023},
journal = {IEEE J. Solid State Circuits},
author = {{Yoshisato Yokoyama} and {Koji Nii} and {Yuichiro Ishii} and {Shinji Tanaka} and {Kazutoshi Kobayashi}}
}