Multilingual phrase-based concordance generation in real-time. - Kumiko Tanaka-Ishii; Yuichiro Ishii (Inf. Retr., 2007)

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. - Yasumasa Tsukamoto; Takeshi Kida; T. Yamaki; Yuichiro Ishii; Koji Nii; Koji Tanaka; Shinji Tanaka; Yuji Kihara (CICC, 2011)

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. - Yuichiro Ishii; Hidehiro Fujiwara; Shinji Tanaka; Yasumasa Tsukamoto; Koji Nii; Yuji Kihara; Kazumasa Yanagisawa (IEEE J. Solid State Circuits, 2011)

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. - Koji Nii; Yasumasa Tsukamoto; Yuichiro Ishii; Makoto Yabuuchi; Hidehiro Fujiwara; Kazuyoshi Okamoto (Asian Test Symposium, 2012)

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. - Yuichiro Ishii; Yasumasa Tsukamoto; Koji Nii; Hidehiro Fujiwara; Makoto Yabuuchi; Koji Tanaka; Shinji Tanaka; Yasuhisa Shimazaki (ISSCC, 2012)

A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Yasumasa Tsukamoto; Yuichiro Ishii; Tetsuya Matsumura; Yoshio Matsuda (ISQED, 2013)

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues. - Yoshisato Yokoyama; Yuichiro Ishii; Koji Tanaka; Tatsuya Fukuda; Yoshiki Tsujihashi; Atsushi Miyanishi; Shinobu Asayama; Keiichi Maekawa; Kazutoshi Shiba; Koji Nii (A-SSCC, 2014)

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU. - Yoshisato Yokoyama; Yuichiro Ishii; Hidemitsu Kojima; Atsushi Miyanishi; Yoshiki Tsujihashi; Shinobu Asayama; Kazutoshi Shiba; Koji Tanaka; Tatsuya Fukuda; Koji Nii; Kazumasa Yanagisawa (ISQED, 2014)

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. - Shinji Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Toshiaki Sano; Koji Tanaka; Yasumasa Tsukamoto; Koji Nii; Hirotoshi Sato (VLSIC, 2014)

A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU. - Yoshisato Yokoyama; Yuichiro Ishii; Toshihiro Inada; Koji Tanaka; Miki Tanaka; Yoshiki Tsujihashi; Koji Nii (A-SSCC, 2015)

A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. - Yuichiro Ishii; Makoto Yabuuchi; Yohei Sawada; Masao Morimoto; Yasumasa Tsukamoto; Yuta Yoshida; Ken Shibata; Toshiaki Sano; Shinji Tanaka; Koji Nii (A-SSCC, 2016)

A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time. - Makoto Yabuuchi; Yohei Sawada; Toshiaki Sano; Yuichiro Ishii; Shinji Tanaka; Miki Tanaka; Koji Nii (VLSI Circuits, 2016)

A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode. - Yoshisato Yokoyama; Yuichiro Ishii; Haruyuki Okuda; Koji Nii (A-SSCC, 2017)

40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications. - Yoshisato Yokoyama; Tomohiro Miura; Yukari Ouchi; Daisuke Nakamura; Jiro Ishikawa; Shunya Nagata; Makoto Yabuuchi; Yuichiro Ishii; Koji Nii (A-SSCC, 2018)

Development of the experimental system that can acquire the gait data online in a quadruped robot. - Yuichiro Ishii; Hiroki Yamamoto; Sungi Kim; Yusuke Ikemoto (MHS, 2018)

Decomposition of Movement Data of Quadruped Robot by Using Autoencoder. - Hiroki Yamamoto; Yuichiro Ishii; Sungi Kim; Yusuke Ikemoto (ROBIO, 2018)

A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU. - Yoshisato Yokoyama; Kenji Goto; Tomohiro Miura; Yukari Ouchi; Daisuke Nakamura; Jiro Ishikawa; Shunya Nagata; Yoshiki Tsujihashi; Yuichiro Ishii (A-SSCC, 2019)

A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit. - Yoshisato Yokoyama; Miki Tanaka; Koji Tanaka; Masao Morimoto; Makoto Yabuuchi; Yuichiro Ishii; Shinji Tanaka (VLSI Circuits, 2020)

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs. - Yoshisato Yokoyama; Yuichiro Ishii; Koji Nii; Kazutoshi Kobayashi (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. - Yumito Aoyagi; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing. - Yoshisato Yokoyama; Koji Nii; Yuichiro Ishii; Shinji Tanaka; Kazutoshi Kobayashi (IEEE J. Solid State Circuits, 2023)

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. - Tomotaka Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Yumito Aoyagi; Masaya Hamada; Kazuto Mizutani; Koji Nii; Hidehiro Fujiwara; Isabel Wang; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. - Yumito Aoyagi; Koji Nii; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2024)

29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme. - Hidehiro Fujiwara; Wei-Chang Zhao; Kinshuk Khare; Yi-Hsin Nien; Chih-Yu Lin; Cheng-Han Lin; Shan-Ru Liao; Kenta Torigoe; Shirleen Xia; Yuichiro Ishii; Yao-Yi Lin; Jhon-Jhy Liaw; et al. (ISSCC, 2025)