Area/delay estimation for digital signal processor cores. - Yuichiro Miyaoka; Yoshiharu Kataoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2001)

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. - Yuichiro Miyaoka; Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS (1), 2002)

A hardware/software partitioning algorithm for SIMD processor cores. - Koichi Tachikake; Nozomu Togawa; Yuichiro Miyaoka; Jinku Choi; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2003)

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. - Nozomu Togawa; Kyosuke Kasahara; Yuichiro Miyaoka; Jinku Choi; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A cosynthesis algorithm for application specific processors with heterogeneous datapaths. - Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

Instruction set and functional unit synthesis for SIMD processor cores. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

A processor core synthesis system in IP-based SoC design. - Naoki Tomono; Shunitsu Kohara; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2005)

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. - Nozomu Togawa; Hideki Kawazu; Jumpei Uchida; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS (4), 2005)

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. - Hideki Kawazu; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Inf. Syst., 2005)

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. - Shunitsu Kohara; Naoki Tomono; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2006)