An Efficient Paired-net Routing Algorithm for High-speed Bipolar LSIs. - Yuichiro Takei; Akira Onozawa; Kenji Kawai; Hitoshi Kitazawa (Great Lakes Symposium on VLSI, 1997)

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. - Keiichi Koike; Kenji Kawai; Akira Onozawa; Yuichiro Takei; Yoshiji Kobayashi; Haruhiko Ichino (IEEE J. Solid State Circuits, 1998)

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. - Kenji Kawai; Keiichi Koike; Yuichiro Takei; Akira Onozawa; Hitoshi Obara; Haruhiko Ichino (IEEE J. Solid State Circuits, 1999)

Prototype ultra wideband-based wireless body area network-consideration of CAP and CFP slot allocation during human walking motion-. - Yuichiro Takei; Hiroki Katsuta; Kenichi Takizawa; Tetsushi Ikegami; Kiyoshi Hamaguchi (EMBC, 2012)