Othello Solver based on a soft-core MIMD processor array. - Takayuki Mabuchi; Takahiro Watanabe; Retsu Moriwaki; Yuji Aoyama; Amarjargal Gundjalam; Yuichiro Yamaji; Hironari Nakada; Minoru Watanabe (FPT, 2010)

A 64-context MEMS optically reconfigurable gate array. - Yuichiro Yamaji; Minoru Watanabe (FPT, 2010)

An FPGA Connect6 Solver with a two-stage pipelined evaluation. - Takahiro Watanabe; Retsu Moriwaki; Yuichiro Yamaji; Yuki Kamikubo; Yuki Torigai; Yuki Nihira; Takashi Yoza; Yumiko Ueno; Yuji Aoyama; Minoru Watanabe (FPT, 2011)

A 144-configuration context MEMS optically reconfigurable gate array. - Yuichiro Yamaji; Minoru Watanabe (SoCC, 2011)

Four-configuration-context optically reconfigurable gate array with a MEMS interleaving method. - Yuichiro Yamaji; Minoru Watanabe (AHS, 2013)

FPGA Blokus Duo Solver using a massively parallel architecture. - Takashi Yoza; Retsu Moriwaki; Yuki Torigai; Yuki Kamikubo; Takayuki Kubota; Takahiro Watanabe; Takumi Fujimori; Hiroyuki Ito; Masato Seo; Kouta Akagi; Yuichiro Yamaji; Minoru Watanabe (FPT, 2013)