An 8-b 800-MHz DAC. - Kazuhisa Nojima; Yuji Gendai (IEEE J. Solid State Circuits, 1990)

A top down mixed-signal design methodology using a mixed-signal simulator and analog HDL. - T. Murayama; Yuji Gendai (EURO-DAC, 1996)

The Maximum-Likelihood Noise Magnitude Estimation in ADC Linearity Measurements. - Yuji Gendai (IEEE Trans. Instrum. Meas., 2010)

A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout. - Takayuki Toyama; Koji Mishina; Koji Tsuchiya; Tatsuya Ichikawa; Hiroyuki Iwaki; Yuji Gendai; Hirotaka Murakami; Kenichi Takamiya; Hiroshi Shiroshita; Yoshinori Muramatsu; Toshihiro Furusawa (ISSCC, 2011)

A Specific Distortion Pattern of Flash ADCs Identified by Discriminating Time-Domain Analysis. - Yuji Gendai; Akira Matsuzawa (IEEE Trans. Instrum. Meas., 2012)

Systematic Construction of Resistor Ladder Network for N-ary DACs. - Manato Hirai; Shuhei Yamamoto; Hirotaka Arai; Anna Kuwana; Hiroshi Tanimoto; Yuji Gendai; Haruo Kobayashi 001 (ASICON, 2019)

Innovative Test Practices in Japan. - Yusuke Asada; Takahiko Shimizu; Yuji Gendai; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Jiang-Lin Wei; Nene Kushita; Hirotaka Arai; Anna Kuwana; Takayuki Nakatani; et al. (VTS, 2019)

Nonlinearity Analysis of Resistive Ladder-Based Current-Steering Digital-to-Analog Converter. - Manato Hirai; Hiroshi Tanimoto; Yuji Gendai; Shuhei Yamamoto; Anna Kuwana; Haruo Kobayashi 001 (ISOCC, 2020)

Back to the Analog Neural Network and Linear Circuit Theory. - Haruo Kobayashi 001; Manato Hirai; Kakeru Otomo; Shogo Katayama; Xueyan Bai; Masashi Chiba; Zifei Xu; Dan Yao; Lengkhang Nengvang; Minh Tri Tran 001; Kanji Yoshihiro; Anna Kuwana; et al. (ASICON, 2023)

A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs. - Shunichi Kubo; Yuji Gendai; Satoshi Miura; Shinsuke Hara; Satoru Tanoi; Akifumi Kasarnatsu; Takeshi Yoshida; Satoshi Tanaka; Shuhei Arnakawa; Minoru Fujishlrna (CICC, 2024)