A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Yuuichi Hirano; Toshiaki Iwamatsu; Yuji Kihara (ISSCC, 2010)

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. - Yasumasa Tsukamoto; Takeshi Kida; T. Yamaki; Yuichiro Ishii; Koji Nii; Koji Tanaka; Shinji Tanaka; Yuji Kihara (CICC, 2011)

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. - Yuichiro Ishii; Hidehiro Fujiwara; Shinji Tanaka; Yasumasa Tsukamoto; Koji Nii; Yuji Kihara; Kazumasa Yanagisawa (IEEE J. Solid State Circuits, 2011)

Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis. - Takeshi Kida; Yasumasa Tsukamoto; Yuji Kihara (ISQED, 2012)