Challenges in Evaluations for a Typical-Case Design Methodology. - Yuji Kunitake; Akihiro Chiyonobu; Koichiro Tanaka; Toshinori Sato (ISQED, 2007)

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM. - Toshinori Sato; Yuji Kunitake (ISQED, 2007)

Exploiting Input Variations for Energy Reduction. - Toshinori Sato; Yuji Kunitake (PATMOS, 2007)

AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. - Tohru Ishihara; Seiichiro Yamaguchi; Yuriko Ishitobi; Tadayuki Matsumura; Yuji Kunitake; Yuichiro Oyama; Yusuke Kaneda; Masanori Muroyama; Toshinori Sato (SASP, 2008)

Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. - Yuji Kunitake; Kazuhiro Mima; Toshinori Sato; Hiroto Yasuura (IEICE Trans. Electron., 2009)

Signal probability control for relieving NBTI in SRAM cells. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura (ISQED, 2010)

A Replacement Strategy for Canary Flip-Flops. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura (PRDC, 2010)

Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura (IEICE Trans. Electron., 2011)

Guidelines for mitigating NBTI degradation in on-chip memories. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; Takanori Hayashida (ISCIT, 2012)

A Selective Replacement Method for Timing-Error-Predicting flip-Flops. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; Takanori Hayashida (J. Circuits Syst. Comput., 2012)