A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. - Takanori Saeki; Yuji Nakaoka; Mamoru Fujita; Akihito Tanaka; Kyoichi Nagata; Kenichi Sakakibara; Tatsuya Matano; Yukio Hoshino; Kazutaka Miyano; Satoshi Isa; Shigeyuki Nakazawa; Eiichiro Kakehashi; et al. (IEEE J. Solid State Circuits, 1996)

System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV. - Kouichi Kumagai; Changqi Yang; Hitoshi Izumino; Nobuyuki Narita; Keisuke Shinjo; Shin-ichi Iwashita; Yuji Nakaoka; Tomohiro Kawamura; Hideo Komabashiri; Tsukasa Minato; Atsushi Ambo; Takamasa Suzuki; et al. (ISSCC, 2006)

Vehicle-in-the-Loop Testing - a Comparative Study for Efficient Validation of ADAS/AD Functions. - Christian Schyr; Hideo Inoue; Yuji Nakaoka (ICCVE, 2022)