An intelligent subprocessor for hardware emulation with 20-MOPS performance. - Hideo Nakamura; Terumi Sawase; Yasushi Akao; Shigeki Masumura; Makoto Hayashi; Hiroshi Ohsuga; Yuji Satoh; Tatsuya Aizawa (IEEE J. Solid State Circuits, 1991)

A 2.9mW, +/- 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration. - Yuji Satoh; Hiroyuki Kobayashi; Takeshi Miyaba; Shouhei Kousai (VLSIC, 2014)

A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems. - Yuta Tsubouchi; Daisuke Miyashita; Yuji Satoh; Takashi Toi; Fumihiko Tachibana; Makoto Morimoto; Junji Wadatsumi; Jun Deguchi (VLSI Circuits, 2018)

A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi (ISSCC, 2019)

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. - Yuta Tsubouchi; Daisuke Miyashita; Takashi Toi; Yuji Satoh; Fumihiko Tachibana; Junji Wadatsumi; Makoto Morimoto; Ryuichi Fujimoto; Jun Deguchi (IEEE J. Solid State Circuits, 2019)

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi; et al. (IEEE J. Solid State Circuits, 2022)