A 256-Mb SDRAM using a register-controlled digital DLL. - Atsushi Hatakeyama; Hirohiko Mochizuki; Tadao Aikawa; Masato Takita; Yuki Ishii; Hironobu Tsuboi; Shin-ya Fujioka; Shusaku Yamaguchi; Makoto Koga; Yuji Serizawa; Koichi Nishimura; Kuninori Kawabata; et al. (IEEE J. Solid State Circuits, 1997)

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line. - Satoshi Eto; Masato Matsumiya; Masato Takita; Yuki Ishii; Toshikazu Nakamura; Kuninori Kawabata; Hideki Kano; Ayako Kitamoto; Toshimi Ikeda; Toru Koga; Mitsuhiro Higashiho; Yuji Serizawa; et al. (IEEE J. Solid State Circuits, 1998)