VLSI Parallel Computer with Data Transfer Network: ADENA. - Hiroshi Kadota; Katsuyuki Kaneko; Yuji Tanikawa; Tatsuo Nogi (ICPP (1), 1989)

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit. - Katsuyuki Kaneko; Tadashi Okamoto; Masaitsu Nakajima; Yasuhiro Nakakura; Satoshi Gokita; Junji Nishikawa; Yuji Tanikawa; Hiroshi Kadota (IEEE J. Solid State Circuits, 1989)