A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. - Tetsushi Koide; Hans Jürgen Mattausch; Yuji Yano; Takayuki Gyohten; Yoshihiro Soda (ASP-DAC, 2003)

Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. - Yuji Yano; Tetsushi Koide; Hans Jürgen Mattausch (ASP-DAC, 2004)

Deterministic High Density Packet-Buffer System for Low Cost Network Systems. - Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Koji Yamamoto 002; Shingo Ata; Kazunari Inoue (AINA, 2012)

Multi-bit sigma-delta TDC architecture with self-calibration. - Satoshi Uemori; Masamichi Ishii; Haruo Kobayashi 001; Yuta Doi; Osamu Kobayashi; Tatsuji Matsuura; Kiichi Niitsu; Yuta Arakawa; Daiki Hirabayashi; Yuji Yano; Tatsuhiro Gake; Nobukazu Takai; et al. (APCCAS, 2012)

A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. - Yasuto Kuroda; Yuji Yano; Hisashi Iwamoto; Koji Yamamoto 002; Kazunari Inoue; Masahiro Suzuki (CICC, 2012)

A slice structure using the management of network traffic prediction for green IT. - Yuji Yano; Hisashi Iwamoto; Yasuto Kuroda; Shiro Ohtani; Shingo Ata; Kazunari Inoue (HPSR, 2012)

2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving. - Kenzo Okuda; Shingo Ata; Yasuto Kuroda; Yuji Yano; Hisashi Iwamoto; Kazunari Inoue; Ikuo Oka (CCNC, 2013)

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. - Satoshi Uemori; Masamichi Ishii; Haruo Kobayashi 001; Daiki Hirabayashi; Yuta Arakawa; Yuta Doi; Osamu Kobayashi; Tatsuji Matsuura; Kiichi Niitsu; Yuji Yano; Tatsuhiro Gake; Takahiro J. Yamaguchi; et al. (J. Electron. Test., 2013)

Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS. - Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Koji Yamamoto 002; Shingo Ata; Kazunari Inoue (IEICE Trans. Commun., 2013)

A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application. - Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Koji Yamamoto 002; Kazunari Inoue; Ikuo Oka (IEICE Trans. Electron., 2013)

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. - Isamu Hayashi; Teruhiko Amano; Naoya Watanabe; Yuji Yano; Yasuto Kuroda; M. Shirata; Katsumi Dosaka; Koji Nii; Hideyuki Noda; Hiroyuki Kawai (IEEE J. Solid State Circuits, 2013)

A study on micro level traffic prediction for energy-aware routers. - Sou Koyano; Shingo Ata; Hisashi Iwamoto; Yuji Yano; Yasuto Kuroda; Kazunari Inoue; Ikuo Oka (ACM SIGOPS Oper. Syst. Rev., 2013)

Behavior extraction from tweets using character N-gram models. - Yuji Yano; Tomonori Hashiyama; Junko Ichino; Shun'ichi Tano (FUZZ-IEEE, 2014)

Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure. - Masami Nawa; Kenzo Okuda; Shingo Ata; Yasuto Kuroda; Yuji Yano; Hisashi Iwamoto; Kazunari Inoue; Ikuo Oka (CCNC, 2016)

A large scale access-control list for IoT security comprising embedded IP-core and DDR DRAM. - Kazunari Inoue; Yuji Yano (ISOCC, 2016)

Demonstration of 100 Gbps optical packet switching using header processor based on 48-bit longest prefix matching. - Hideaki Furukawa; Hiroaki Harai; Yasuto Kuroda; Yuji Yano; Shoji Koyama (Photonic Netw. Commun., 2016)

A 5-ms Error, 22-μA Photoplethysmography Sensor using Current Integration Circuit and Correlated Double Sampling. - Yuji Yano (EMBC, 2018)

Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring. - Yuki Nishikawa; Shintaro Izumi; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2018)

Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis. - Koichi Kajihara; Shintaro Izumi; Seiya Yoshida; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (SiPS, 2018)

An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. - Yuji Yano; Seiya Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Tetsuya Hirose; Masaya Miyahara; Teruki Someya; Kenichi Okada 001; Ippei Akita; Yoshihiko Kurui; Hideyuki Tomizawa; Masahiko Yoshimoto (A-SSCC, 2019)

A Heartbeat Interval Error Compensation Method Using Multiple Linear Regression for Photoplethysmography Sensors. - Seiya Yoshida; Shintaro Izumi; Yuki Nishikawa; Kento Watanabe; Kana Sasai; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (BioCAS, 2019)

A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit. - Kana Sasai; Shintaro Izumi; Kento Watanabe; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE SENSORS, 2019)

Low-Noise Photoplethysmography Sensor Using Correlated Double Sampling for Heartbeat Interval Acquisition. - Kento Watanabe; Shintaro Izumi; Kana Sasai; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Biomed. Circuits Syst., 2019)

Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things. - Seiya Yoshida; Shintaro Izumi; Koichi Kajihara; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. - Daisuke Watanabe; Yuji Yano; Shintaro Izumi; Hiroshi Kawaguchi 001; Kiyoshi Takeuchi; Toshiro Hiramoto; Shoichi Iwai; Masami Murakata; Masahiko Yoshimoto (AICAS, 2020)

Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors. - Kento Watanabe; Shintaro Izumi; Yuji Yano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Commun., 2020)

28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. - Yuji Yano; Hisashi Iwamoto; Takuma Yoshimura; Yoshihiro Nishida; Tatsuya Mori; Kiyotaka Komoku; Hidekuni Takao; Kazutami Arimoto (VLSI-DAT, 2022)