40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications. - Yoshisato Yokoyama; Tomohiro Miura; Yukari Ouchi; Daisuke Nakamura; Jiro Ishikawa; Shunya Nagata; Makoto Yabuuchi; Yuichiro Ishii; Koji Nii (A-SSCC, 2018)

A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU. - Yoshisato Yokoyama; Kenji Goto; Tomohiro Miura; Yukari Ouchi; Daisuke Nakamura; Jiro Ishikawa; Shunya Nagata; Yoshiki Tsujihashi; Yuichiro Ishii (A-SSCC, 2019)