Automatic communication synthesis with hardware sharing for design space exploration. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (ISCAS, 2010)

Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation. - Seiya Shibata; Yuki Ando; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Fast design space exploration for mixed hardware-software embedded systems. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (ISOCC, 2011)

A Fast Performance Estimation Framework for System-Level Design Space Exploration. - Seiya Shibata; Yuki Ando; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (IESS, 2013)

Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs. - Yuki Ando; Seiya Shibata; Shinya Honda; Hiroyuki Tomiyama; Hiroaki Takada (FCCM, 2014)

A Case Study of FPGA Blokus Duo Solver by System-Level Design. - Yuki Ando; Masataka Ogawa; Yuya Mizoguchi; Kouta Kumagai; Miaw Torng-Der; Shinya Honda (SIGARCH Comput. Archit. News, 2014)

Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip. - Yuki Ando; Yukihito Ishida; Shinya Honda; Hiroaki Takada; Masato Edahiro (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler. - Yuki Ando; Shinya Honda; Hiroaki Takada; Masato Edahiro (J. Inf. Process., 2015)

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. - Shusuke Kawai; Hiromitsu Aoyama; Rui Ito; Yutaka Shimizu; Mitsuyuki Ashida; Asuka Maki; Tomohiko Takeuchi; Hiroyuki Kobayashi; Go Urakawa; Hiroaki Hoshino; Shigehito Saigusa; Kazushi Koyama; et al. (ISSCC, 2018)

An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer. - Shusuke Kawai; Rui Ito; Kengo Nakata; Yutaka Shimizu; Motoki Nagata; Tomohiko Takeuchi; Hiroyuki Kobayashi; Katsuyuki Ikeuchi; Takayuki Kato; Yosuke Hagiwara; Yuki Fujimura; Kentaro Yoshioka; et al. (IEEE J. Solid State Circuits, 2018)

Kinematics Analysis and Tracking Control of Novel Single Actuated Lizard Type Robot. - Shunsuke Nansai; Yuki Ando; Norihiro Kamamichi; Hiroshi Itoh (SMC, 2020)