A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test. - Yuki Fukazawa; Tsuyoshi Iwagaki; Hideyuki Ichihara; Tomoo Inoue (Asian Test Symposium, 2013)

A fault tolerant response analyzer with self-error-correction capability. - Yuki Fukazawa; Hideyuki Ichihara; Tomoo Inoue (ETS, 2015)

Register Port Prediction for a Banked Register File. - Hiroaki Kawashima; Takahiro Sasaki; Yuki Fukazawa; Toshio Kondo (CANDAR, 2015)

An Architectural Framework of Snoopy Interconnection for Heterogeneous Cache Systems. - Seiji Miyoshi; Takahiro Sasaki; Yuki Fukazawa; Toshio Kondo (CANDAR, 2015)

A cache memory with unit tile and line accessibility. - BaoKang Wang; Yuki Fukazawa; Toshio Kondo; Takahiro Sasaki (ICIS, 2016)

A Rapid Verification Framework for Developing Multi-core Processor. - Kouki Kayamuro; Takahiro Sasaki; Yuki Fukazawa; Toshio Kondo (CANDAR, 2016)

SIMD-based datapath with efficient operation structure for motion estimation. - Yuki Fukazawa; Keita Watanabe; Yuki Minoura; Toshio Kondo; Takahiro Sasaki (ICASSP, 2016)

Tile/line access cache memory based on a multi-level Z-order tiling data layout. - BaoKang Wang; Yuki Fukazawa; Toshio Kondo; Takahiro Sasaki (Concurr. Comput. Pract. Exp., 2018)