Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. - Shunsuke Okumura; Yohei Nakata; Koji Yanagida; Yuki Kagiyama; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2011)

Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. - Masahiro Yoshikawa; Shunsuke Okumura; Yohei Nakata; Yuki Kagiyama; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2011)

7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. - Shunsuke Okumura; Yuki Kagiyama; Yohei Nakata; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Bit error rate estimation in SRAM considering temperature fluctuation. - Yuki Kagiyama; Shunsuke Okumura; Koji Yanagida; Shusuke Yoshimoto; Yohei Nakata; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2012)

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. - Shunsuke Okumura; Yohei Nakata; Koji Yanagida; Yuki Kagiyama; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Electron. Express, 2012)