An FPGA Connect6 Solver with a two-stage pipelined evaluation. - Takahiro Watanabe; Retsu Moriwaki; Yuichiro Yamaji; Yuki Kamikubo; Yuki Torigai; Yuki Nihira; Takashi Yoza; Yumiko Ueno; Yuji Aoyama; Minoru Watanabe (FPT, 2011)

Gray-level image recognition on a dynamically reconfigurable vision architecture. - Yuki Kamikubo; Minoru Watanabe; Shoji Kawahito (SoCC, 2012)

Image recognition operation on a dynamically reconfigurable vison architecture. - Yuki Kamikubo; Minoru Watanabe; Shoji Kawahito (FPL, 2013)

FPGA Blokus Duo Solver using a massively parallel architecture. - Takashi Yoza; Retsu Moriwaki; Yuki Torigai; Yuki Kamikubo; Takayuki Kubota; Takahiro Watanabe; Takumi Fujimori; Hiroyuki Ito; Masato Seo; Kouta Akagi; Yuichiro Yamaji; Minoru Watanabe (FPT, 2013)

Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture. - Yuki Kamikubo; Minoru Watanabe; Shoji Kawahito (ISCAS, 2014)