Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. - Ji Chel Bea; Mariappan Murugesan; Yuki Ohara; Akihiro Noriki; Hisashi Kino; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

3D integration technology for 3D stacked retinal chip. - Yoshiyuki Kaiho; Yuki Ohara; Hirotaka Takeshita; Kouji Kiyoyama; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

A parallel ADC for high-speed CMOS image processing system with 3D structure. - Kouji Kiyoyama; Yuki Ohara; Kang Wook Lee 002; Y. Yang; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

Heterogeneous integration technology for MEMS-LSI multi-chip module. - Kang Wook Lee 002; Shigeyuki Kanno; Yuki Ohara; Kouji Kiyoyama; Ji Chel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. - Yuki Ohara; Akihiro Noriki; Katsuyuki Sakuma; Kang Wook Lee 002; Mariappan Murugesan; Jichoel Bea; Fumiaki Yamada; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. - Mariappan Murugesan; Yuki Ohara; Jichoel Bea; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

Temporary bonding strength control for self-assembly-based 3D integration. - Takafumi Fukushima; Yuki Ohara; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs. - Kang Wook Lee 002; Jichoel Bea; Takafumi Fukushima; Yuki Ohara; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration. - Yuki Ohara; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)