A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. - Aravind Tharayil Narayanan; Makihiko Katsuragi; Kengo Nakata; Yuki Terashima; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2016)

A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. - Dongsheng Yang 002; Tomohiro Ueno; Wei Deng 001; Yuki Terashima; Kengo Nakata; Aravind Tharayil Narayanan; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2016)

8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. - Huy Cu Ngo; Kengo Nakata; Toru Yoshioka; Yuki Terashima; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2017)

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (ISSCC, 2017)

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (IEEE J. Solid State Circuits, 2019)

A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS. - Yun Wang 008; Bangan Liu; Rui Wu 001; Hanli Liu; Aravind Tharayil Narayanan; Jian Pang; Ning Li 009; Toru Yoshioka; Yuki Terashima; Haosheng Zhang; Dexian Tang; Makihiko Katsuragi; et al. (IEEE J. Solid State Circuits, 2019)